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* Added support for REMRodrigo Alejandro Melo2017-12-011-1/+1
| | | | | It works as MOD. MOD is bad implemented, but useful when the two operand has the same sign.
* Fixed scientific notation when the sign of the exponent is usedRodrigo Alejandro Melo2017-12-011-0/+2
| | | | Removed the testcase of todo.vhd.
* Add testcase for underscore in NATURALLarry Doolittle2017-11-281-1/+2
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* Added support to entity instantiationsRodrigo Alejandro Melo2017-11-281-0/+4
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* Don't ship translated_examples/todo.vLarry Doolittle2017-11-271-50/+0
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* Moved unsupported commented things to todo.vhdRodrigo Alejandro Melo2017-11-274-5/+50
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* sort lists in MakefilesLarry Doolittle2017-11-271-1/+1
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* Examples: match case of module name in filenameLarry Doolittle2017-11-261-0/+0
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* Renamed generic to withselectRodrigo Alejandro Melo2017-11-261-1/+1
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* Renamed while to whileloopRodrigo Alejandro Melo2017-11-261-1/+1
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* Renamed gh_fifo_async16_sr to fifoRodrigo Alejandro Melo2017-11-261-5/+4
| | | | And clean up of trailer tabs and spaces.
* Renamed generate to forgen and for to forloopRodrigo Alejandro Melo2017-11-262-2/+2
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* Merge pull request #8 from ldoolitt/excludeRodrigo A. Melo2017-11-262-8/+2
|\ | | | | Implemented a mechanism to exclude files in the main Makefile
| * Changed translated_examples/Makefile to analyze individually againRodrigo Alejandro Melo2017-11-261-6/+2
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| * Simplified iverilog checkRodrigo Alejandro Melo2017-11-242-4/+2
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* | Fixed partselect exampleRodrigo Alejandro Melo2017-11-261-1/+1
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* | Correct selection of -: vs. +:Larry Doolittle2017-11-254-26/+28
| | | | | | | | | | Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd
* | Add missing CONVFUNC_1 to grammarLarry Doolittle2017-11-241-1/+3
| | | | | | | | Allows completion of dsp.vhd changes from previous commit
* | Turn off debug prints and fix warningsLarry Doolittle2017-11-232-7/+16
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* | First stupid attempt to finish part selectLarry Doolittle2017-11-234-30/+37
| | | | | | | | | | No attempt to figure out -: vs. +: Already yields much better results on test files
* | Added partselect exampleRodrigo Alejandro Melo2017-11-231-0/+27
|/ | | | The conversion to Verilog must be fixed.
* Allow second argument to CONVFUNC_2 to be exprLarry Doolittle2017-11-221-1/+1
| | | | | Adds one more shift/reduce conflict. Include test case.
* Experimental support of exponentiationRodrigo Alejandro Melo2017-11-211-0/+4
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* Adding support for while loopLarry Doolittle2017-11-201-0/+26
| | | | | Supplied by jeinstei Labelling of the loop is still unsupported.
* Simple fix to genericmap exampleLarry Doolittle2017-11-181-2/+2
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* Fix capitalization of iverilogLarry Doolittle2017-11-171-1/+1
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* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-171-0/+14
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* Removed extra parentheses when parentheses are usedRodrigo Alejandro Melo2017-11-172-2/+2
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* Removed unuseful parenthesesRodrigo Alejandro Melo2017-11-178-39/+39
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* Parentheses were removed for CONVFUNC_1 (ex. to_integer)Rodrigo Alejandro Melo2017-11-171-2/+2
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* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-161-2/+2
| | | | Added an example that fail to todo.vhd.
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-161-2/+2
| | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd.
* Changes on translated_examples (dsp and ifchain2) due to previous changes in ↵Rodrigo Alejandro Melo2017-11-162-2/+2
| | | | examples
* Squelch some trailing whitespaceLarry Doolittle2017-11-121-4/+4
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* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-104-4/+83
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* New make target: verilogcheckLarry Doolittle2017-11-102-0/+25
| | | | | | | Requires iverilog to operate. Scans resulting files in translated_examples directory. This patch includes some simple fixes to reduce the number of errors reported, but there are more that need further investigation.
* New rem before END PROCESSLarry Doolittle2017-11-101-0/+36
| | | | With test case!
* Experiment with OTHERS logicLarry Doolittle2017-11-091-0/+16
| | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code!
* Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-194-8/+7
| | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog.
* Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-191-1/+1
| | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed.
* Modified to use ',' to separate sensitivity list in verilog 2001Rodrigo Alejandro Melo2017-02-177-19/+19
| | | | Changes applied to translated_examples.
* Changed translated_examples due that Verilog 2001 is now the defaultRodrigo Alejandro Melo2017-02-1713-455/+162
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* Added command line option --quietRodrigo Alejandro Melo2017-02-1713-273/+0
| | | | | Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples.
* Added analysis of examples with GHDLRodrigo Alejandro Melo2017-02-145-14/+14
| | | | | | | | Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented.
* Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-091-0/+36
| | | | | Also support was added for real numbers especially thinking in generics. Files called scientific.vhd and scientific.v were added for test.
* Space deleted in the <size>'<radix><number> notationRodrigo Alejandro Melo2017-02-0911-246/+246
| | | | | | | It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified.
* vhd2vl-2.5Larry Doolittle2015-09-2012-24/+24
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* vhd2vl-2.4Larry Doolittle2015-09-2012-68/+107
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* vhd2vl-2.3Larry Doolittle2015-09-2012-22/+244
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* vhd2vl-2.2Larry Doolittle2015-09-2011-0/+1727
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