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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-24 05:58:32 -0800 |
|---|---|---|
| committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-24 05:58:32 -0800 |
| commit | 7aa0f8b9184dbc921e50529f5acefbfad70cb5b7 (patch) | |
| tree | 113c209265a5fc67d7050d379360e00bcf81a63d /translated_examples | |
| parent | b4a19aee6840dfecc26a0db7eec3c85211440c38 (diff) | |
| download | vhdl2vl-7aa0f8b9184dbc921e50529f5acefbfad70cb5b7.tar.gz vhdl2vl-7aa0f8b9184dbc921e50529f5acefbfad70cb5b7.zip | |
Add missing CONVFUNC_1 to grammar
Allows completion of dsp.vhd changes from previous commit
Diffstat (limited to 'translated_examples')
| -rw-r--r-- | translated_examples/dsp.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v index 71e44dd..fe4331e 100644 --- a/translated_examples/dsp.v +++ b/translated_examples/dsp.v @@ -26,13 +26,15 @@ parameter [31:0] bus_width=24; wire foo; reg [63:0] sr; +wire [31:0] iparam; + assign iparam = param; always @(posedge clk) begin // dout <= std_logic_vector(to_unsigned(1,bus_width)); if(we == 1'b1) begin sr <= {sr[thing_size - bus_width - 1:0],din}; end - dout <= sr[param * bus_width + bus_width - 1+:bus_width - 1 + 1]; + dout <= sr[iparam * bus_width + bus_width - 1+:bus_width - 1 + 1]; end |

