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authorRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-16 11:16:29 -0300
committerRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-16 11:16:29 -0300
commit44413311fbd9ca45cf769014990c1b99df2c330c (patch)
tree6284f9bdcc38f66d1464c0e19973010766d9257a /translated_examples
parent194af658cd6a9021999d5e416a7a0a04d8dc4fa8 (diff)
downloadvhdl2vl-44413311fbd9ca45cf769014990c1b99df2c330c.tar.gz
vhdl2vl-44413311fbd9ca45cf769014990c1b99df2c330c.zip
Changes on translated_examples (dsp and ifchain2) due to previous changes in examples
Diffstat (limited to 'translated_examples')
-rw-r--r--translated_examples/dsp.v2
-rw-r--r--translated_examples/ifchain2.v2
2 files changed, 2 insertions, 2 deletions
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v
index c91fbcd..23ac529 100644
--- a/translated_examples/dsp.v
+++ b/translated_examples/dsp.v
@@ -27,7 +27,7 @@ parameter [31:0] bus_width=24;
wire foo;
always @(clk) begin
- dout <= 1'b1;
+ dout <= ((1));
end
diff --git a/translated_examples/ifchain2.v b/translated_examples/ifchain2.v
index 53e223d..0510f84 100644
--- a/translated_examples/ifchain2.v
+++ b/translated_examples/ifchain2.v
@@ -11,7 +11,7 @@ output reg result
reg [3:0] counter;
-parameter CLK_DIV_VAL = 11;
+parameter CLK_DIV_VAL = (11);
always @(posedge clk, posedge rstn) begin
if((rstn == 1'b0)) begin
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