Renamed generate to forgen and for to forloop

2 files changed, 2 insertions, 2 deletions

diff --git a/translated_examples/generate.v b/translated_examples/forgen.v
index b96a6b3..96be6cf 100644
--- a/translated_examples/generate.v
+++ b/translated_examples/forgen.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module gen(
+module forgen(
 input wire sysclk,
 input wire reset,
 input wire wrb,
diff --git a/translated_examples/for.v b/translated_examples/forloop.v
index ce31bc7..88ee5f7 100644
--- a/translated_examples/for.v
+++ b/translated_examples/forloop.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module forp(
+module forloop(
 input wire reset,
 input wire sysclk
 );