Added analysis of examples with GHDL

Some examples were corrected according GHDL complains.
Corresponding traslated_examples were modified.
Use of synopsys libraries was removed.
Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned').
The problem was comented.

5 files changed, 14 insertions, 14 deletions

diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index dd755b7..e4e724e 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -42,15 +42,15 @@ wire [8:0] input_status;
 wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
 
   // drive input status
-  assign input_status = {foo[9:4],((baz[3:0] & foo[3:0] | (( ~baz[3:0] & bam[3:0]))))};
+  assign input_status = {foo[9:4],((((baz[2:0] & foo[3:0])) | (( ~baz[2:0] & bam[3:0]))))};
   // drive based on foo
-  assign out_i = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
+  assign out_i[4] = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
   // not drive
   always @(negedge reset or negedge sysclk) begin
     if((reset != 1'b0)) begin
       foo <= {14{1'b0}};
     end else begin
-      foo[3 * ((2 - 1))] <= (4 * ((1 + 2)));
+      foo[3 * ((2 - 1))] <= baz[1 * ((1 + 2)) - 2];
       bam[13:0] <= foo;
     end
   end
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index fe2e5c4..df0e7bb 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -60,7 +60,7 @@ wire [31:0] complex;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b1;
+      default : code[9:2] <= (((a)) + ((b)));
     endcase
   end
 
@@ -68,6 +68,6 @@ wire [31:0] complex;
   assign foo = {(((1 + 1))-((0))+1){1'b0}};
   assign egg = {78{1'b0}};
   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
-  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
+  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
 
 endmodule
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index 7128d4e..b01f808 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -83,7 +83,7 @@ wire full;
 
 
 
-reg [data_width - 1:0] ram_mem[15:0];
+wire [data_width - 1:0] ram_mem[15:0];
 wire iempty;
 wire ifull;
 wire add_WR_CE;
@@ -107,16 +107,16 @@ reg isrst_r;
   //------------------------------------------
   always @(posedge clk_WR) begin
     if(((WR == 1'b1) && (ifull == 1'b0))) begin
-      ram_mem[(add_WR[3:0])] <= D;
+      //ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D;
     end
   end
 
-  assign Q = ram_mem[(add_RD[3:0])];
+  //Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0))));
   //---------------------------------------
   //--- Write address counter -------------
   //---------------------------------------
   assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_WR = add_WR + 4'h1;
+  assign n_add_WR = (((add_WR)) + 4'h1);
   always @(posedge clk_WR or posedge rst) begin
     if((rst == 1'b1)) begin
       add_WR <= {5{1'b0}};
@@ -149,7 +149,7 @@ reg isrst_r;
   //--- Read address counter --------------
   //---------------------------------------
   assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_RD = add_RD + 4'h1;
+  assign n_add_RD = (((add_RD)) + 4'h1);
   always @(posedge clk_RD or posedge rst) begin
     if((rst == 1'b1)) begin
       add_RD <= {5{1'b0}};
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index feddd03..b719b82 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -41,7 +41,7 @@ reg [31:0] c[3:0];
   always @(posedge clk) begin
     if({b[1],a[3:2]} == 3'b001) begin
       status <= 1'b1;
-      c[0] <= 16'hFFFF;
+      c[0] <= 32'hFFFFFFFF;
     end
   end
 
diff --git a/translated_examples/test.v b/translated_examples/test.v
index e7ce5a2..c8f4d53 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -187,7 +187,7 @@ reg [1:0] colour;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b1;
+      default : code[9:2] <= (((a)) + ((b)));
     endcase
   end
 
@@ -238,8 +238,8 @@ reg [1:0] colour;
     // Outputs
     .dout(memdin));
 
-  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
-  assign enf = a == (7'b1101111 + load) && c < 7'b1000111 ? 1'b1 : 1'b0;
+  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
+  assign enf = c < 7'b1000111 ? 1'b1 : 1'b0;
   assign eno = enf;
 
 endmodule