Fixes in examples and translated examples to avoid some complains of iVerilog

'test' was repeated as entity/module name
'config' was used as port name and is a reserved word in Verilog.

4 files changed, 7 insertions, 8 deletions

diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index c436e64..c195ad2 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module test(
+module generic1(
 input wire reset,
 input wire sysclk,
 input wire [bus_width:0] a,
diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index e09865f..578f491 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module test(
+module genericmap(
 input wire clk,
 input wire rstn,
 input wire en,
@@ -10,7 +10,6 @@ input wire [25:0] din,
 input wire we,
 input wire [7:0] pixel_in,
 input wire pix_req,
-input wire config,
 input wire bip,
 input wire [7:0] a,
 input wire [7:0] b,
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index ad22a8d..e037889 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module test(
+module ifchain(
 input wire clk,
 input wire rstn
 );
diff --git a/translated_examples/test.v b/translated_examples/test.v
index aa3fe85..97e79ac 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -16,7 +16,7 @@ input wire [25:0] din,
 input wire we,
 input wire [7:0] pixel_in,
 input wire pix_req,
-input wire config,
+input wire config1,
 input wire bip,
 input wire [7:0] a,
 input wire [7:0] b,
@@ -59,7 +59,7 @@ wire [5:0] memaddr;
 wire [13:0] memdout;
 reg [1:0] colour;
 
-  assign param = config == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3;
+  assign param = config1 == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3;
   // Synchronously process
   always @(posedge clk) begin
     pixel_out <= pixel_in ^ 8'b11001100;
@@ -127,13 +127,13 @@ reg [1:0] colour;
 
   assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
   // Asynch process
-  always @(we, addr, config, bip) begin
+  always @(we, addr, config1, bip) begin
     if(we == 1'b1) begin
       if(addr[2:0] == 3'b100) begin
         selection <= 1'b1;
       end
       else if(({b,a}) == {a,b} && bip == 1'b0) begin
-        selection <= config;
+        selection <= config1;
       end
       else begin
         selection <= 1'b1;