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authorRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-21 13:22:39 -0300
committerRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-11-21 13:22:39 -0300
commit9023ec57a1d34bffd6d331a26877dacd37d5ca4f (patch)
tree7f095d70771085dd73018d67c3a5b2b0378be65e /translated_examples
parent696301f0a1dbdbe42a2813e767afbfd571942669 (diff)
downloadvhdl2vl-9023ec57a1d34bffd6d331a26877dacd37d5ca4f.tar.gz
vhdl2vl-9023ec57a1d34bffd6d331a26877dacd37d5ca4f.zip
Experimental support of exponentiation
Diffstat (limited to 'translated_examples')
-rw-r--r--translated_examples/expr.v4
1 files changed, 4 insertions, 0 deletions
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index cf4fd53..d6691ea 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -6,15 +6,18 @@ input wire sysclk,
input wire ival
);
+parameter [31:0] SIZE=2 ** 8 - 1;
+parameter SIZE_OF = 2 ** 8 - 1;
reg [13:0] foo;
wire [2:0] baz;
reg [22:0] bam;
wire [5:3] out_i;
wire [8:0] input_status;
wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
+wire [2 ** 3 - 1:0] expo;
// drive input status
assign input_status = {foo[9:4],(baz[2:0] & foo[3:0]) | ( ~baz[2:0] & bam[3:0])};
@@ -30,5 +33,6 @@ wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
end
end
+ //expo <= std_logic_vector(to_unsigned(2**4, 2**8));
endmodule
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