Removed unuseful parentheses

8 files changed, 39 insertions, 39 deletions

diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index b975ef3..36dfdb8 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -102,17 +102,17 @@ wire [31:0] g_sys_in_ii;
 wire [31:0] g_dout_i;
 
   // qaz out
-  assign g_zaq_out_i = ((g_secondary_t_l_dout & ((g_aux ^ g_style_t_y_dout)))) | ((g_alu_l_dout & alu_u &  ~g_secondary_t_l_dout)) | (( ~g_alu_l_dout &  ~g_secondary_t_l_dout & g_t_u_dout));
+  assign g_zaq_out_i = (g_secondary_t_l_dout & (g_aux ^ g_style_t_y_dout)) | (g_alu_l_dout & alu_u &  ~g_secondary_t_l_dout) | ( ~g_alu_l_dout &  ~g_secondary_t_l_dout & g_t_u_dout);
   // Changed
   assign g_zaq_out = g_zaq_out_i &  ~g_t_jkl_sink_l_dout;
   // qaz 
   // JLB
-  assign g_zaq_ctl_i =  ~((((g_t_l_dout &  ~g_t_jkl_sink_l_dout)) | ((g_t_l_dout & g_t_jkl_sink_l_dout &  ~g_zaq_out_i))));
+  assign g_zaq_ctl_i =  ~((g_t_l_dout &  ~g_t_jkl_sink_l_dout) | (g_t_l_dout & g_t_jkl_sink_l_dout &  ~g_zaq_out_i));
   // mux
   //vnavigatoroff
   assign g_zaq_ctl = scanb == 1'b1 ? g_zaq_ctl_i : 32'b00000000000000000000000000000000;
   //vnavigatoron
-  assign g_zaq_hhh_enb =  ~((g_t_hhh_l_dout));
+  assign g_zaq_hhh_enb =  ~(g_t_hhh_l_dout);
   assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout;
   assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout;
   // Dout
@@ -287,12 +287,12 @@ wire [31:0] g_dout_i;
   // switch
   assign g_zaq_in_y = g_style_t_y_dout ^ q2_g_zaq_in;
   // qaz
-  assign g_style_vfr_dout = {g_zaq_in_y[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])))};
+  assign g_style_vfr_dout = {g_zaq_in_y[31:4],(g_style_c_l_dout[3:0] & q_g_zaq_in_cd) | ( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])};
   // in scan mode
-  assign g_zaq_in_y_no_dout = scanb == 1'b1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout;
+  assign g_zaq_in_y_no_dout = scanb == 1'b1 ? g_style_t_y_dout ^ g_zaq_in : g_style_t_y_dout;
   //vnavigatoron
-  assign g_sys_in_i = ({g_zaq_in_y_no_dout[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])))});
-  assign g_sys_in_ii = ((g_sys_in_i &  ~gwerthernal_style_l_dout)) | ((gwerthernal_style_u_dout & gwerthernal_style_l_dout));
+  assign g_sys_in_i = {g_zaq_in_y_no_dout[31:4],(g_style_c_l_dout[3:0] & q_g_zaq_in_cd) | ( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])};
+  assign g_sys_in_ii = (g_sys_in_i &  ~gwerthernal_style_l_dout) | (gwerthernal_style_u_dout & gwerthernal_style_l_dout);
   assign g_sys_in = g_sys_in_ii;
   always @(posedge reset, posedge sysclk) begin
     if((reset != 1'b0)) begin
@@ -344,7 +344,7 @@ wire [31:0] g_dout_i;
   end
 
   // generate
-  assign g_n_active = (((((q_g_style_vfr_dout &  ~g_style_vfr_dout)) | (( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout))))) & g_n_l_dout;
+  assign g_n_active = ((q_g_style_vfr_dout &  ~g_style_vfr_dout) | ( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout)) & g_n_l_dout;
   // check for lqq active and set lqq vfr register
   // also clear
   always @(posedge reset, posedge sysclk) begin
@@ -405,7 +405,7 @@ wire [31:0] g_dout_i;
           g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
         end
         else begin
-          g_vector[8 * i + 7:8 * i] <= (((g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8])) + ((imod8)));
+          g_vector[8 * i + 7:8 * i] <= (g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8]) + (imod8);
         end
       end
     end
diff --git a/translated_examples/counters.v b/translated_examples/counters.v
index 8aa1eac..3a68b34 100644
--- a/translated_examples/counters.v
+++ b/translated_examples/counters.v
@@ -76,12 +76,12 @@ reg prev_do_file_card;
 
   //---
   // form the outputs
-  assign wfoo0_llwln = (wfoo0_llwln_var);
-  assign debct = (debct_var);
-  assign Z0 = (Z0_var);
-  assign Y1 = (Y1_var);
-  assign X2 = (X2_var);
-  assign W3 = (W3_var);
+  assign wfoo0_llwln = wfoo0_llwln_var;
+  assign debct = debct_var;
+  assign Z0 = Z0_var;
+  assign Y1 = Y1_var;
+  assign X2 = X2_var;
+  assign W3 = W3_var;
   assign Z0_cwm = Z0_cwm_i;
   assign Y1_cwm = Y1_cwm_i;
   assign X2_cwm = X2_cwm_i;
@@ -120,7 +120,7 @@ reg prev_do_file_card;
       //--
       //  wfoo0
       if(wfoo0_baz == 1'b1) begin
-        wfoo0_llwln_var <= (wfoo0_turn);
+        wfoo0_llwln_var <= wfoo0_turn;
         main_wfoo0_cwm <= 1'b0;
         if(wfoo0_llwln_var == 32'b00000000000000000000000000000000) begin
           do_q3p_wfoo0 <= 1'b0;
@@ -133,7 +133,7 @@ reg prev_do_file_card;
         if(do_q3p_wfoo0 == 1'b1 && wfoo0_blrb == 1'b1) begin
           wfoo0_llwln_var <= wfoo0_llwln_var - 1;
           if((wfoo0_llwln_var == 32'b00000000000000000000000000000000)) begin
-            wfoo0_llwln_var <= (wfoo0_turn);
+            wfoo0_llwln_var <= wfoo0_turn;
             if(main_wfoo0_cwm == 1'b0) begin
               wfoo0_cwm <= 1'b1;
               main_wfoo0_cwm <= 1'b1;
@@ -150,7 +150,7 @@ reg prev_do_file_card;
       end
       if(Z0_baz == 1'b1) begin
         // counter Baz
-        Z0_var <= (Z0_turn);
+        Z0_var <= Z0_turn;
         if(Z0_turn == 32'b00000000000000000000000000000000) begin
           do_q3p_Z0 <= 1'b0;
         end
@@ -175,7 +175,7 @@ reg prev_do_file_card;
             Z0_var <= Z0_var - 1;
             if((Z0_var == 32'b00000000000000000000000000000000)) begin
               Z0_cwm_i <= 1'b1;
-              Z0_var <= (Z0_turn);
+              Z0_var <= Z0_turn;
             end
           end
           // Z0_bar
@@ -187,7 +187,7 @@ reg prev_do_file_card;
       end
       if(Y1_baz == 1'b1) begin
         // counter Baz
-        Y1_var <= (Y1_turn);
+        Y1_var <= Y1_turn;
         if(Y1_turn == 32'b00000000000000000000000000000000) begin
           do_q3p_Y1 <= 1'b0;
         end
@@ -211,7 +211,7 @@ reg prev_do_file_card;
           Y1_var <= Y1_var - 1;
           if((Y1_var == 32'b00000000000000000000000000000000)) begin
             Y1_cwm_i <= 1'b1;
-            Y1_var <= (Y1_turn);
+            Y1_var <= Y1_turn;
           end
         end
         // Y1_bar
@@ -222,7 +222,7 @@ reg prev_do_file_card;
       end
       if(X2_baz == 1'b1) begin
         // counter Baz
-        X2_var <= (X2_turn);
+        X2_var <= X2_turn;
         if(X2_turn == 32'b00000000000000000000000000000000) begin
           do_q3p_X2 <= 1'b0;
         end
@@ -247,7 +247,7 @@ reg prev_do_file_card;
           if((X2_var == 32'b00000000000000000000000000000000)) begin
             //{
             X2_cwm_i <= 1'b1;
-            X2_var <= (X2_turn);
+            X2_var <= X2_turn;
           end
         end
         //X2_bar
@@ -258,7 +258,7 @@ reg prev_do_file_card;
       end
       if(W3_baz == 1'b1) begin
         // counter Baz
-        W3_var <= (W3_turn);
+        W3_var <= W3_turn;
         if(W3_turn == 32'b00000000000000000000000000000000) begin
           do_q3p_W3 <= 1'b0;
         end
@@ -283,7 +283,7 @@ reg prev_do_file_card;
           if((W3_var == 32'b00000000000000000000000000000000)) begin
             //{
             W3_cwm_i <= 1'b1;
-            W3_var <= (W3_turn);
+            W3_var <= W3_turn;
           end
         end
         // W3_bar
@@ -294,7 +294,7 @@ reg prev_do_file_card;
       end
       if(debct_baz == 1'b1) begin
         // counter Baz
-        debct_var <= (debct_turn);
+        debct_var <= debct_turn;
         if(debct_turn == 32'b00000000000000000000000000000000) begin
           do_q3p_debct <= 1'b0;
         end
@@ -324,7 +324,7 @@ reg prev_do_file_card;
             //{
             debct_cwm_i <= 1'b1;
             debct_pull <= 1'b1;
-            debct_var <= (debct_turn);
+            debct_var <= debct_turn;
           end
         end
         // debct_bar
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v
index 23ac529..52474d3 100644
--- a/translated_examples/dsp.v
+++ b/translated_examples/dsp.v
@@ -27,7 +27,7 @@ parameter [31:0] bus_width=24;
 wire foo;
 
   always @(clk) begin
-    dout <= ((1));
+    dout <= 1;
   end
 
 
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index 2fb8849..bf1a529 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -17,9 +17,9 @@ wire [8:0] input_status;
 wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
 
   // drive input status
-  assign input_status = {foo[9:4],((((baz[2:0] & foo[3:0])) | (( ~baz[2:0] & bam[3:0]))))};
+  assign input_status = {foo[9:4],(baz[2:0] & foo[3:0]) | ( ~baz[2:0] & bam[3:0])};
   // drive based on foo
-  assign out_i[4] = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
+  assign out_i[4] = (enable & (aux ^ outy)) | (debug & dv &  ~enable) | ( ~debug &  ~enable & value);
   // not drive
   always @(negedge reset, negedge sysclk) begin
     if((reset != 1'b0)) begin
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index c195ad2..e523dfc 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -29,7 +29,7 @@ wire [31:0] complex;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= (((a)) + ((b)));
+      default : code[9:2] <= (a) + (b);
     endcase
   end
 
@@ -37,6 +37,6 @@ wire [31:0] complex;
   assign foo = {(((1 + 1))-((0))+1){1'b0}};
   assign egg = {78{1'b0}};
   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
-  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
+  assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001};
 
 endmodule
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index 1aacf25..84a75d9 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -75,7 +75,7 @@ reg isrst_r;
   //--- Write address counter -------------
   //---------------------------------------
   assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_WR = (((add_WR)) + 4'h1);
+  assign n_add_WR = (add_WR) + 4'h1;
   always @(posedge clk_WR, posedge rst) begin
     if((rst == 1'b1)) begin
       add_WR <= {5{1'b0}};
@@ -108,7 +108,7 @@ reg isrst_r;
   //--- Read address counter --------------
   //---------------------------------------
   assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_RD = (((add_RD)) + 4'h1);
+  assign n_add_RD = (add_RD) + 4'h1;
   always @(posedge clk_RD, posedge rst) begin
     if((rst == 1'b1)) begin
       add_RD <= {5{1'b0}};
@@ -132,8 +132,8 @@ reg isrst_r;
         add_RD_GCwc[0] <= n_add_RD[0] ^ n_add_RD[1];
         add_RD_GCwc[1] <= n_add_RD[1] ^ n_add_RD[2];
         add_RD_GCwc[2] <= n_add_RD[2] ^ n_add_RD[3];
-        add_RD_GCwc[3] <= n_add_RD[3] ^ (( ~n_add_RD[4]));
-        add_RD_GCwc[4] <= ( ~n_add_RD[4]);
+        add_RD_GCwc[3] <= n_add_RD[3] ^ ( ~n_add_RD[4]);
+        add_RD_GCwc[4] <=  ~n_add_RD[4];
       end
       else begin
         add_RD <= add_RD;
diff --git a/translated_examples/ifchain2.v b/translated_examples/ifchain2.v
index 0510f84..53e223d 100644
--- a/translated_examples/ifchain2.v
+++ b/translated_examples/ifchain2.v
@@ -11,7 +11,7 @@ output reg result
 
 
 reg [3:0] counter;
-parameter CLK_DIV_VAL = (11);
+parameter CLK_DIV_VAL = 11;
 
   always @(posedge clk, posedge rstn) begin
     if((rstn == 1'b0)) begin
diff --git a/translated_examples/test.v b/translated_examples/test.v
index 351191a..be4d6b3 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -121,7 +121,7 @@ reg [1:0] colour;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= (((a)) + ((b)));
+      default : code[9:2] <= (a) + (b);
     endcase
   end
 
@@ -172,7 +172,7 @@ reg [1:0] colour;
     // Outputs
     .dout(memdin));
 
-  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
+  assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001};
   assign enf = c < 7'b1000111 ? 1'b1 : 1'b0;
   assign eno = enf;