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authorRodrigo A. Melo <rmelo@inti.gob.ar>2017-11-26 10:23:42 -0300
committerGitHub <noreply@github.com>2017-11-26 10:23:42 -0300
commitde11eaa7fecd61199cf38104900069c5a1fec8b6 (patch)
treef096f07d857c74cea2ed94012a0f9ad4f439d597 /translated_examples
parent730564e3837dd6f056c7d2b5e0d197cc1cf01a32 (diff)
parent4d76e5796e9bcaf5b615ffe6050b2811bad0f97d (diff)
downloadvhdl2vl-de11eaa7fecd61199cf38104900069c5a1fec8b6.tar.gz
vhdl2vl-de11eaa7fecd61199cf38104900069c5a1fec8b6.zip
Merge pull request #8 from ldoolitt/exclude
Implemented a mechanism to exclude files in the main Makefile
Diffstat (limited to 'translated_examples')
-rw-r--r--translated_examples/Makefile8
-rw-r--r--translated_examples/ifchain2.v2
2 files changed, 2 insertions, 8 deletions
diff --git a/translated_examples/Makefile b/translated_examples/Makefile
index 6ab476d..88f5081 100644
--- a/translated_examples/Makefile
+++ b/translated_examples/Makefile
@@ -1,14 +1,8 @@
#!/usr/bin/make
-TEMP = ../temp/verilog
-
all:
ifneq ($(shell which iverilog),)
- @mkdir -p $(TEMP)
@echo "##### Checking resulting Verilog files with iverilog ###########"
- @-cd $(TEMP); $(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\
+ @$(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\
iverilog -Wall -y . -t null $(VERILOG);)
endif
-
-clean:
- rm -fr $(TEMP)
diff --git a/translated_examples/ifchain2.v b/translated_examples/ifchain2.v
index 53e223d..3208dcf 100644
--- a/translated_examples/ifchain2.v
+++ b/translated_examples/ifchain2.v
@@ -1,6 +1,6 @@
// no timescale needed
-module ifchain(
+module ifchain2(
input wire clk,
input wire rstn,
input wire enable,
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