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* Take two files out of exclude listLarry Doolittle2017-11-271-2/+0
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* Moved unsupported commented things to todo.vhdRodrigo Alejandro Melo2017-11-274-4/+14
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* Examples: match case of module name in filenameLarry Doolittle2017-11-261-0/+0
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* Renamed generic to withselectRodrigo Alejandro Melo2017-11-261-3/+4
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* Renamed while to whileloopRodrigo Alejandro Melo2017-11-261-4/+3
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* Deleted from todo.vhd a testcase that now is supportedRodrigo Alejandro Melo2017-11-261-4/+1
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* Renamed gh_fifo_async16_sr to fifoRodrigo Alejandro Melo2017-11-261-18/+16
| | | | And clean up of trailer tabs and spaces.
* Unexcluded partselectRodrigo Alejandro Melo2017-11-261-2/+1
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* Renamed generate to forgen and for to forloopRodrigo Alejandro Melo2017-11-262-14/+17
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* Merge pull request #8 from ldoolitt/excludeRodrigo A. Melo2017-11-262-3/+7
|\ | | | | Implemented a mechanism to exclude files in the main Makefile
| * Renamed .exclude to excludeRodrigo Alejandro Melo2017-11-251-0/+0
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| * Removed Makefile from examples/.excludeRodrigo Alejandro Melo2017-11-241-1/+0
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| * Implemented a mechanism to exclude files in the main MakefileRodrigo Alejandro Melo2017-11-241-0/+5
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| * Simplified iverilog checkRodrigo Alejandro Melo2017-11-241-3/+3
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* | Fixed partselect exampleRodrigo Alejandro Melo2017-11-261-2/+2
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* | Correct selection of -: vs. +:Larry Doolittle2017-11-251-1/+3
| | | | | | | | | | Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd
* | Add missing CONVFUNC_1 to grammarLarry Doolittle2017-11-241-1/+1
| | | | | | | | Allows completion of dsp.vhd changes from previous commit
* | Fixed dsp.vhdRodrigo Alejandro Melo2017-11-241-13/+15
| | | | | | | | There is a new problem (commented).
* | Turn off debug prints and fix warningsLarry Doolittle2017-11-232-2/+7
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* | First stupid attempt to finish part selectLarry Doolittle2017-11-234-5/+12
| | | | | | | | | | No attempt to figure out -: vs. +: Already yields much better results on test files
* | Added partselect exampleRodrigo Alejandro Melo2017-11-231-0/+30
|/ | | | The conversion to Verilog must be fixed.
* Allow second argument to CONVFUNC_2 to be exprLarry Doolittle2017-11-221-1/+1
| | | | | Adds one more shift/reduce conflict. Include test case.
* Experimental support of exponentiationRodrigo Alejandro Melo2017-11-211-1/+8
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* Adding support for while loopLarry Doolittle2017-11-201-0/+28
| | | | | Supplied by jeinstei Labelling of the loop is still unsupported.
* Align the prototypes for dsp in dsp and genericmapLarry Doolittle2017-11-202-4/+3
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* Beginning support for assertionsLarry Doolittle2017-11-181-0/+1
| | | | Based on work by jeinstei
* Simple fix to genericmap exampleLarry Doolittle2017-11-181-2/+2
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* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-171-1/+3
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* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-161-2/+6
| | | | Added an example that fail to todo.vhd.
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-162-5/+24
| | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd.
* The resulting files of the GHDL analysis were moved to temp/vhdlRodrigo Alejandro Melo2017-11-161-2/+5
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* Added the special file examples/todo.vhdRodrigo Alejandro Melo2017-11-161-0/+20
| | | | | | The idea is to put there things that don't work or that could be improved. Is ignored in the main Makefile when target 'translate' is used. The target 'todo' was added to the main Makefile.
* Examples were corrected according to GHDL complainsRodrigo Alejandro Melo2017-11-165-8/+10
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* Squelch some trailing whitespaceLarry Doolittle2017-11-124-17/+16
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* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-104-7/+94
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* New make target: verilogcheckLarry Doolittle2017-11-102-0/+23
| | | | | | | Requires iverilog to operate. Scans resulting files in translated_examples directory. This patch includes some simple fixes to reduce the number of errors reported, but there are more that need further investigation.
* New rem before END PROCESSLarry Doolittle2017-11-101-0/+32
| | | | With test case!
* Experiment with OTHERS logicLarry Doolittle2017-11-091-0/+17
| | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code!
* Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-194-14/+14
| | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog.
* Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-191-1/+1
| | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed.
* Added analysis of examples with GHDLRodrigo Alejandro Melo2017-02-1413-33/+37
| | | | | | | | Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented.
* Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-091-0/+13
| | | | | Also support was added for real numbers especially thinking in generics. Files called scientific.vhd and scientific.v were added for test.
* vhd2vl-2.4Larry Doolittle2015-09-201-0/+3
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* vhd2vl-2.3Larry Doolittle2015-09-201-0/+205
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* vhd2vl-2.2Larry Doolittle2015-09-2011-0/+1314
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