Align the prototypes for dsp in dsp and genericmap

2 files changed, 3 insertions, 4 deletions

diff --git a/examples/dsp.vhd b/examples/dsp.vhd
index cf0bfc7..7eda7c1 100644
--- a/examples/dsp.vhd
+++ b/examples/dsp.vhd
@@ -6,8 +6,7 @@ USE IEEE.numeric_std.all;
 entity dsp is generic(
   rst_val   : std_logic := '0';
   thing_size: integer := 201;
-  bus_width : integer := 24
-);
+  bus_width : integer := 24);
     port(
       -- Inputs
       clk, rstn : in std_logic;
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 39db71e..c5275ba 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -34,14 +34,14 @@ architecture rtl of genericmap is
     generic(
       rst_val   : std_logic := '0';
       thing_size: integer := 201;
-      bus_width : integer := 22);
+      bus_width : integer := 24);
     port(
       -- Inputs
       clk, rstn : in std_logic;
       en, start : in std_logic;
       param : in std_logic_vector(7 downto 0);
       addr : in std_logic_vector(2 downto 0);
-      din : in std_logic_vector(25 downto 0);
+      din : in std_logic_vector(bus_width-1 downto 0);
       we : in std_logic;
       memdin : out std_logic_vector(13 downto 0);
       -- Outputs