diff options
author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-10 17:53:09 -0800 |
---|---|---|
committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-10 17:53:09 -0800 |
commit | 5e431b2052690866e0fa102bb8e880d0ac21f575 (patch) | |
tree | 539c62695a91128f374b960cbd3abbc21b4454e6 /examples | |
parent | e6b83c5bc077ab2060f2df8850d49ca1f7bbc398 (diff) | |
download | vhdl2vl-5e431b2052690866e0fa102bb8e880d0ac21f575.tar.gz vhdl2vl-5e431b2052690866e0fa102bb8e880d0ac21f575.zip |
New rem before END PROCESS
With test case!
Diffstat (limited to 'examples')
-rw-r--r-- | examples/ifchain2.vhd | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/examples/ifchain2.vhd b/examples/ifchain2.vhd new file mode 100644 index 0000000..09794b1 --- /dev/null +++ b/examples/ifchain2.vhd @@ -0,0 +1,32 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +entity ifchain is port( + clk, rstn : in std_logic; + result: out std_logic +); +end ifchain; + +architecture rtl of ifchain is + signal counter : std_logic_vector(3 downto 0); +begin + +clk_src : process(clk, rstn) is +begin + if (rstn = '0') then + counter <= (others => '0'); + result <= '0'; + elsif (rising_edge(clk)) then -- Divide by 2 by default + if (enable = '1') then + if (counter = 0) then + counter <= CLK_DIV_VAL; + result <= '1'; + else + counter <= counter - 1; + result <= '0'; + end if; -- counter + end if; -- enable + end if; -- clk, rst_n +end process clk_src; + +end rtl; |