First stupid attempt to finish part select

No attempt to figure out -: vs. +:
Already yields much better results on test files

4 files changed, 12 insertions, 5 deletions

diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
index 3fc1d9d..cdaf51f 100644
--- a/examples/bigfile.vhd
+++ b/examples/bigfile.vhd
@@ -227,7 +227,7 @@ begin
               -- set
               g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
             else
-              exit;
+              -- XXX not ready for exit;
             end if;
           --vnavigatoroff
           else
diff --git a/examples/dsp.vhd b/examples/dsp.vhd
index 7eda7c1..4f139d5 100644
--- a/examples/dsp.vhd
+++ b/examples/dsp.vhd
@@ -25,8 +25,15 @@ end;
 
 architecture rtl of dsp is
     signal foo : std_logic;
+    signal sr : std_logic_vector(63 downto 0);
 begin
     process(clk) begin
-       dout <= std_logic_vector(to_unsigned(1,bus_width));
+       -- dout <= std_logic_vector(to_unsigned(1,bus_width));
+       if rising_edge(clk) then
+           if we = '1' then
+               sr <= sr(thing_size-bus_width-1 downto 0) & din;
+           end if;
+           dout <= sr(param*bus_width+bus_width-1 downto param*bus_width);
+       end if;
     end process;
 end rtl;
diff --git a/examples/for.vhd b/examples/for.vhd
index c18c2e3..71ff3a5 100644
--- a/examples/for.vhd
+++ b/examples/for.vhd
@@ -12,7 +12,7 @@ architecture rtl of forp is
 begin
   TIMERS :
   process(reset, sysclk)
-    variable timer_var : integer:= 0;
+    variable timer_var : integer; -- XXX unhandled := 0;
     variable a, i, j, k : integer;
     variable zz5 : std_logic_vector(31 downto 0);
     variable zz : std_logic_vector(511 downto 0);
diff --git a/examples/partselect.vhd b/examples/partselect.vhd
index 14b6520..25279dd 100644
--- a/examples/partselect.vhd
+++ b/examples/partselect.vhd
@@ -15,14 +15,14 @@ begin
 
    test_i: process(clk_i)
       variable big_var : std_logic_vector(31 downto 0);
-      variable j       : integer:=8;
+      variable j       : integer; -- XXX not ready for :=8;
    begin
       if rising_edge(clk_i) then
          big_sig(31 downto 24) <= big_sig(7 downto 0);
          big_var(31 downto 24) := big_var(7 downto 0);
          lit_sig(24 to 31)     <= lit_sig(0 to 7);
          --
-         big_sig(i*3+8 downto i*3) <= big_sig(i-1 downto 0);
+         big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0);
          big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0);
       end if;
    end process test_i;