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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-27 15:02:39 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-11-27 15:02:39 -0300 |
| commit | 6683eeba0e6956dc6bcb4ff967791cd125584dbc (patch) | |
| tree | fb5e38be7b9689aa81de48f7e85c317f2655210c /examples | |
| parent | b544184b93e5fdacadab0c69a0cbfabe6fd22192 (diff) | |
| download | vhdl2vl-6683eeba0e6956dc6bcb4ff967791cd125584dbc.tar.gz vhdl2vl-6683eeba0e6956dc6bcb4ff967791cd125584dbc.zip | |
Moved unsupported commented things to todo.vhd
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/bigfile.vhd | 2 | ||||
| -rw-r--r-- | examples/forloop.vhd | 2 | ||||
| -rw-r--r-- | examples/partselect.vhd | 2 | ||||
| -rw-r--r-- | examples/todo.vhd | 12 |
4 files changed, 14 insertions, 4 deletions
diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd index a9624ba..5897f16 100644 --- a/examples/bigfile.vhd +++ b/examples/bigfile.vhd @@ -227,8 +227,6 @@ begin if( n9_bit_write = '1' ) then -- set g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1'; - else - -- XXX not ready for exit; end if; --vnavigatoroff else diff --git a/examples/forloop.vhd b/examples/forloop.vhd index 241b8c7..492ec27 100644 --- a/examples/forloop.vhd +++ b/examples/forloop.vhd @@ -13,7 +13,7 @@ architecture rtl of forloop is begin TIMERS : process(reset, sysclk) - variable timer_var : integer; -- XXX unhandled := 0; + variable timer_var : integer; variable a, i, j, k : integer; variable zz5 : std_logic_vector(31 downto 0); variable zz : std_logic_vector(511 downto 0); diff --git a/examples/partselect.vhd b/examples/partselect.vhd index 86dc073..90c67b2 100644 --- a/examples/partselect.vhd +++ b/examples/partselect.vhd @@ -16,7 +16,7 @@ begin test_i: process(clk_i) variable big_var : std_logic_vector(31 downto 0); variable lit_var : std_logic_vector(0 to 31); - variable j : integer; -- XXX not ready for :=8; + variable j : integer; begin if rising_edge(clk_i) then big_sig(31 downto 24) <= big_sig(7 downto 0); diff --git a/examples/todo.vhd b/examples/todo.vhd index 0144597..c0cdbd9 100644 --- a/examples/todo.vhd +++ b/examples/todo.vhd @@ -4,6 +4,7 @@ use IEEE.numeric_std.all; entity todo is port ( + clk_i : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); @@ -19,6 +20,17 @@ begin --************************************************************************** -- Wrong translations --************************************************************************** + -- + test_i: process(clk_i) + -- iverilog: variable declaration assignments are only allowed at the module level. + variable i : integer:=8; + begin + for i in 0 to 7 loop + if i=4 then + exit; -- iverilog: error: malformed statement + end if; + end loop; + end process test_i; --************************************************************************** -- Translations which abort with syntax error (uncomment to test) |
