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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-24 05:58:32 -0800 |
|---|---|---|
| committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-24 05:58:32 -0800 |
| commit | 7aa0f8b9184dbc921e50529f5acefbfad70cb5b7 (patch) | |
| tree | 113c209265a5fc67d7050d379360e00bcf81a63d /examples | |
| parent | b4a19aee6840dfecc26a0db7eec3c85211440c38 (diff) | |
| download | vhdl2vl-7aa0f8b9184dbc921e50529f5acefbfad70cb5b7.tar.gz vhdl2vl-7aa0f8b9184dbc921e50529f5acefbfad70cb5b7.zip | |
Add missing CONVFUNC_1 to grammar
Allows completion of dsp.vhd changes from previous commit
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/dsp.vhd | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/dsp.vhd b/examples/dsp.vhd index 6bc762f..a762a4e 100644 --- a/examples/dsp.vhd +++ b/examples/dsp.vhd @@ -28,7 +28,7 @@ architecture rtl of dsp is signal sr : std_logic_vector(63 downto 0); signal iparam : integer; begin - --iparam <= to_integer(unsigned(param)); + iparam <= to_integer(unsigned(param)); process(clk) begin -- dout <= std_logic_vector(to_unsigned(1,bus_width)); if rising_edge(clk) then |

