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authorRodrigo Alejandro Melo <rodrigomelo9@gmail.com>2017-11-26 11:01:42 -0300
committerRodrigo Alejandro Melo <rodrigomelo9@gmail.com>2017-11-26 11:01:42 -0300
commit32fe8418c53a7a3341c7e66d947fbc368a2eb4b9 (patch)
treee58f3f5a87b16035f38b4313810c447bce9c6551 /examples
parent96afe7f205ef153fedb9bf1ae6b41f189ce16f62 (diff)
downloadvhdl2vl-32fe8418c53a7a3341c7e66d947fbc368a2eb4b9.tar.gz
vhdl2vl-32fe8418c53a7a3341c7e66d947fbc368a2eb4b9.zip
Renamed while to whileloop
Diffstat (limited to 'examples')
-rw-r--r--examples/whileloop.vhd (renamed from examples/while.vhd)7
1 files changed, 3 insertions, 4 deletions
diff --git a/examples/while.vhd b/examples/whileloop.vhd
index 5d2ee9e..44793e3 100644
--- a/examples/while.vhd
+++ b/examples/whileloop.vhd
@@ -2,16 +2,15 @@ library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity whilep is port(
+entity whileloop is port(
A : in integer;
Z : out std_logic_vector(3 downto 0)
);
-end whilep;
+end whileloop;
-architecture rtl of whilep is
+architecture rtl of whileloop is
begin
-
process (A)
variable I : integer range 0 to 4;
begin
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