Squelch some trailing whitespace

4 files changed, 16 insertions, 17 deletions

diff --git a/examples/generate.vhd b/examples/generate.vhd
index 4abdbf6..30246c1 100644
--- a/examples/generate.vhd
+++ b/examples/generate.vhd
@@ -8,7 +8,6 @@ entity gen is   generic(
                   sysclk, reset, wrb : in std_logic;
                   din : in std_logic_vector(bus_width downto 0);
                   rdout: out std_logic_vector(bus_width downto 0)
-                  
 );
 end gen;
 architecture rtl of gen is
diff --git a/examples/generic.vhd b/examples/generic.vhd
index 8a12b50..10c2d0e 100644
--- a/examples/generic.vhd
+++ b/examples/generic.vhd
@@ -25,7 +25,7 @@ begin
                         (others => '0') when "011",
                         std_logic_vector(unsigned(a) + unsigned(b)) when others;
   code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
-  
+
   foo <= (others => '0');
   egg <= (others => '0');
   baz <= (others => '1');
diff --git a/examples/mem.vhd b/examples/mem.vhd
index 90c1d62..7b96b65 100644
--- a/examples/mem.vhd
+++ b/examples/mem.vhd
@@ -16,14 +16,14 @@ generic(
     din : in unsigned(bus_width-1 downto 0);
     dout : out unsigned(bus_width-1 downto 0)
   );
-end entity; 
+end entity;
 
 architecture rtl of mem is
   type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0);
   signal mem : mem_Type;
   signal al : unsigned(addr_width-1 downto 0) := X"00";
 begin
-  dout <= mem(al);  
+  dout <= mem(al);
   process (clk) is
   begin
     if rising_edge(clk) then
diff --git a/examples/test.vhd b/examples/test.vhd
index d102a11..3729b09 100644
--- a/examples/test.vhd
+++ b/examples/test.vhd
@@ -1,7 +1,7 @@
--- Project: VHDL to Verilog RTL translation 
--- Revision: 1.0 
--- Date of last Revision: February 27 2001 
--- Designer: Vincenzo Liguori 
+-- Project: VHDL to Verilog RTL translation
+-- Revision: 1.0
+-- Date of last Revision: February 27 2001
+-- Designer: Vincenzo Liguori
 -- vhd2vl test file
 -- This VHDL file exercises vhd2vl
 
@@ -32,7 +32,7 @@ entity test is port(
   code1 : out std_logic_vector(9 downto 0);
   complex : out std_logic_vector(23 downto 0);
   eno : out std_logic
-);  
+);
 end test;
 
 architecture rtl of test is
@@ -66,7 +66,7 @@ component mem port(
   -- Outputs
   dout : out std_logic_vector(13 downto 0)
 );
-end component;  
+end component;
 
   type state is (red, green, blue, yellow);
   signal status : state;
@@ -86,14 +86,14 @@ begin
 
   -- Synchronously process
   process(clk) begin
-    if clk'event and clk = '1' then 
+    if clk'event and clk = '1' then
       pixel_out <= pixel_in xor "11001100";
     end if;
   end process;
 
   -- Synchronous process
   process(clk) begin
-    if rising_edge(clk) then 
+    if rising_edge(clk) then
       case status is
         when red => colour <= "00";
         when green => colour <= "01";
@@ -107,9 +107,9 @@ begin
   process(clk,rstn) begin
     if rstn = '0' then
       status <= red;
-    elsif rising_edge(clk) then 
+    elsif rising_edge(clk) then
       case status is
-        when red => 
+        when red =>
           if pix_req = '1' then
             status <= green;
           end if;
@@ -119,7 +119,7 @@ begin
             status <= blue;
           elsif (b(5) & a(3 downto 2)) = "001" then
             status <= yellow;
-          end if;          
+          end if;
         when blue =>
           status <= yellow;
         when others =>
@@ -137,7 +137,7 @@ begin
                         (others => '0') when "011",
                         std_logic_vector(unsigned(a) + unsigned(b)) when others;
   code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
-  
+
   -- Asynch process
   decode : process(we, addr, config1, bip) begin
     if we = '1' then
@@ -170,7 +170,7 @@ begin
     memaddr => memaddr,
     memdout => memdout
   );
-  
+
   dsp_mem : mem port map(
     -- Inputs
     clk => clk,