vhd2vl-2.2

11 files changed, 1314 insertions, 0 deletions

diff --git a/examples/based.vhd b/examples/based.vhd
new file mode 100644
index 0000000..d9b5a29
--- /dev/null
+++ b/examples/based.vhd
@@ -0,0 +1,15 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+
+entity based is port( sysclk : in std_logic);
+end based;
+architecture rtl of based is
+  signal foo,foo2,foo8,foo10,foo11,foo16 : integer;
+begin
+  foo <= 123;
+  foo2 <= 2#00101101110111#;
+  foo8 <= 8#0177362#;
+  foo10<= 10#01234#;
+  foo11<= 11#01234#;
+  foo16<= 16#12af#;
+end rtl;
diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
new file mode 100644
index 0000000..9d76855
--- /dev/null
+++ b/examples/bigfile.vhd
@@ -0,0 +1,465 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+-- CONNECTIVITY DEFINITION
+entity bigfile is
+  port (
+    -- from external pins
+    sysclk : in  std_logic;
+    g_zaq_in : in  std_logic_vector(31 downto 0);
+    g_aux : in  std_logic_vector(31 downto 0);
+    scanb : in  std_logic;
+    g_wrb : in  std_logic;
+    g_rdb : in  std_logic;
+    g_noop_clr : in  std_logic_vector(31 downto 0);
+    swe_ed : in  std_logic;
+    swe_lv : in  std_logic;
+    din : in  std_logic_vector(63 downto 0);
+    g_dout_w0x0f : in  std_logic_vector(4 downto 0);
+    n9_bit_write : in  std_logic;
+    -- from reset_gen block
+    reset : in  std_logic;
+    alu_u : in  std_logic_vector(31 downto 0);
+    debct_ping : in  std_logic;
+    g_sys_in : out std_logic_vector(31 downto 0);
+    g_zaq_in_rst_hold : out std_logic_vector(31 downto 0);
+    g_zaq_hhh_enb : out std_logic_vector(31 downto 0);
+    g_zaq_out : out std_logic_vector(31 downto 0);
+    g_dout : out std_logic_vector(31 downto 0);
+    g_zaq_ctl : out std_logic_vector(31 downto 0);
+    g_zaq_qaz_hb : out std_logic_vector(31 downto 0);
+    g_zaq_qaz_lb : out std_logic_vector(31 downto 0);
+    gwerth : out std_logic_vector(31 downto 0);
+    g_noop : out std_logic_vector(31 downto 0);
+    g_vector : out std_logic_vector(8*32-1 downto 0);
+    swe_qaz1 : out std_logic_vector(31 downto 0)
+    );
+end bigfile;
+
+
+-- IMPLEMENTATION
+architecture rtl of bigfile is
+
+  -- constants 
+  constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000";
+  constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001";
+  constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010";  
+  constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011";
+  constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100";  
+  constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101";
+  constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110";
+  constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111";
+  constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000";
+  constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001";
+  constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010";
+  constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011";
+  constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100";
+  constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101";
+  constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110";
+  constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111";
+  constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000";
+  constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001";
+  constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010";
+  constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011";
+  constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100";
+  constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101";
+  constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110";
+  constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111";
+
+                                                                               -- comment
+  signal g_t_klim_dout : std_logic_vector(31 downto 0);
+  signal g_t_u_dout : std_logic_vector(31 downto 0);
+  signal g_t_l_dout : std_logic_vector(31 downto 0);
+  signal g_t_hhh_l_dout : std_logic_vector(31 downto 0);
+  signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0);
+  signal g_secondary_t_l_dout : std_logic_vector(31 downto 0);
+  signal g_style_c_l_dout : std_logic_vector(3 downto 0);  -- not used
+  signal g_e_z_dout : std_logic_vector(31 downto 0);
+  signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0);
+  signal g_style_vfr_dout : std_logic_vector(31 downto 0);
+  signal g_style_klim_dout : std_logic_vector(31 downto 0);
+  signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0);
+  signal g_style_t_y_dout : std_logic_vector(31 downto 0);
+  signal g_n_l_dout : std_logic_vector(31 downto 0);
+  signal g_n_vfr_dout : std_logic_vector(31 downto 0);
+  signal g_e_n_r_dout : std_logic_vector(31 downto 0);
+  signal g_n_r_bne_dout : std_logic;
+  signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0);
+  signal g_alu_l_dout : std_logic_vector(31 downto 0);
+  signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0);
+  signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0);
+  signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0);
+  signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0);
+  signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0);
+  
+  -- other
+  signal q_g_zaq_in : std_logic_vector(31 downto 0);
+  signal q2_g_zaq_in : std_logic_vector(31 downto 0);
+  signal q3_g_zaq_in : std_logic_vector(31 downto 0);
+  signal q_g_zaq_in_cd : std_logic_vector(3 downto 0);
+  signal q_g_style_vfr_dout : std_logic_vector(31 downto 0);
+  signal q_g_unzq : std_logic_vector(3 downto 0);
+  -- i
+  signal g_n_active : std_logic_vector(31 downto 0);
+
+  -- inter
+  signal g_zaq_in_y : std_logic_vector(31 downto 0);
+  signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0);
+  signal g_zaq_out_i : std_logic_vector(31 downto 0);
+  signal g_zaq_ctl_i : std_logic_vector(31 downto 0);
+  signal g_sys_in_i : std_logic_vector(31 downto 0);
+  signal g_sys_in_ii : std_logic_vector(31 downto 0);
+  signal g_dout_i : std_logic_vector(31 downto 0);
+
+begin
+
+  -- qaz out
+  g_zaq_out_i <=
+    -- if secondary
+    (g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or
+    -- if alu
+    (g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or
+    -- otherwise
+    (not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout);
+  -- Changed
+  g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout;
+  
+  -- qaz 
+  -- JLB
+  g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or
+                    (g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i));
+  -- mux
+  --vnavigatoroff
+  g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000";
+  --vnavigatoron
+  
+  g_zaq_hhh_enb <= not(g_t_hhh_l_dout);
+
+  g_zaq_qaz_hb <= g_t_qaz_mult_high_dout;
+  g_zaq_qaz_lb <= g_t_qaz_mult_low_dout;
+
+
+  -- Dout
+  g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else
+                 g_t_u_dout and g_style_klim_dout                                             when g_dout_w0x0f = g_t_u_w0x0f                else
+                 g_t_l_dout and g_style_klim_dout                                            when g_dout_w0x0f = g_t_l_w0x0f               else
+                 g_t_hhh_l_dout and g_style_klim_dout                                    when g_dout_w0x0f = g_t_hhh_l_w0x0f       else
+                 g_t_jkl_sink_l_dout and g_style_klim_dout                                 when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f    else
+                 g_secondary_t_l_dout and g_style_klim_dout                                  when g_dout_w0x0f = g_secondary_t_l_w0x0f     else
+                 ("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f       else
+                 g_e_z_dout                                                                 when g_dout_w0x0f = g_e_z_w0x0f            else
+                 g_n_both_qbars_l_dout                                                      when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else
+                 g_style_vfr_dout and g_style_klim_dout                                             when g_dout_w0x0f = g_style_vfr_w0x0f                else
+                 g_style_klim_dout                                                                       when g_dout_w0x0f = g_style_klim_w0x0f                  else
+                 g_unklimed_style_vfr_dout                                                            when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f       else
+                 g_style_t_y_dout and g_style_klim_dout                                    when g_dout_w0x0f = g_style_t_y_w0x0f       else
+                 g_n_l_dout                                                                 when g_dout_w0x0f = g_n_l_w0x0f            else
+                 g_n_vfr_dout                                                                 when g_dout_w0x0f = g_n_vfr_w0x0f            else
+                 g_e_n_r_dout                                                            when g_dout_w0x0f = g_e_n_r_w0x0f       else
+                 ("0000000000000000000000000000000" & g_n_r_bne_dout)                      when g_dout_w0x0f = g_n_r_bne_w0x0f       else
+                 g_n_div_rebeq_dout                                                         when g_dout_w0x0f = g_n_div_rebeq_w0x0f    else
+                 g_alu_l_dout and g_style_klim_dout                                             when g_dout_w0x0f = g_alu_l_w0x0f                else
+                 g_t_qaz_mult_low_dout and g_style_klim_dout                                  when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f     else
+                 g_t_qaz_mult_high_dout and g_style_klim_dout                                 when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f    else
+                 gwerthernal_style_u_dout and g_style_klim_dout                                     when g_dout_w0x0f = gwerthernal_style_u_w0x0f        else
+                 g_style_main_reset_hold_dout and g_style_klim_dout                                    when g_dout_w0x0f = g_style_main_reset_hold_w0x0f       else
+                 gwerthernal_style_l_dout and g_style_klim_dout                                    when g_dout_w0x0f = gwerthernal_style_l_w0x0f       else
+                 "00000000000000000000000000000000";
+  g_dout <= g_dout_i when g_rdb = '0' else (others => '1');
+
+
+  -- this  can be used to use zzz1
+  g_style_main_reset_hold_dout_proc :
+  process(sysclk)
+  begin
+    if( sysclk'event and sysclk = '1' ) then
+      if( scanb = '1' ) then
+        if( reset = '1' ) then
+          g_style_main_reset_hold_dout <= g_zaq_in;
+        end if;
+      --vnavigatoroff
+      else 
+        g_style_main_reset_hold_dout <= q2_g_zaq_in;
+      end if;
+      --vnavigatoron
+    end if;
+  end process;
+  -- qaz
+  g_zaq_in_rst_hold <= g_style_main_reset_hold_dout;
+
+  -- Din 
+  g_doutister_proc :
+  process(reset, sysclk)
+    variable g_dout_w0x0f_v : std_logic_vector(4 downto 0);
+  begin
+    if( reset /= '0' ) then
+      g_t_klim_dout                  <= (others => '0');
+      g_t_u_dout                 <= (others => '0');
+      g_t_l_dout                <= (others => '0');
+      g_t_hhh_l_dout        <= (others => '0');
+      g_t_jkl_sink_l_dout     <= (others => '0');
+      g_secondary_t_l_dout      <= (others => '0');
+      g_style_c_l_dout        <= (others => '0');
+      g_e_z_dout             <= (others => '0');
+      g_n_both_qbars_l_dout  <= (others => '0');
+      g_style_klim_dout                   <= (others => '0');
+      g_style_t_y_dout        <= (others => '0');
+      g_n_l_dout             <= (others => '0');
+      g_e_n_r_dout        <= (others => '0');
+      g_n_r_bne_dout        <= '0';
+      g_n_div_rebeq_dout     <= (others => '1');
+      g_alu_l_dout                 <= (others => '0');
+      g_t_qaz_mult_low_dout      <= (others => '1');  -- NOTE Low
+      g_t_qaz_mult_high_dout     <= (others => '0');
+      gwerthernal_style_u_dout         <= (others => '0');      
+      gwerthernal_style_l_dout        <= (others => '0');
+    elsif( sysclk'event and sysclk = '1' ) then
+      -- clear
+      g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr;
+      if( g_wrb = '0' ) then
+        -- because we now...
+        for i in 0 to 1 loop
+          if( i = 0 ) then
+            g_dout_w0x0f_v := g_dout_w0x0f;
+          elsif( i = 1 ) then
+            if( n9_bit_write = '1' ) then
+              -- set
+              g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
+            else
+              exit;
+            end if;
+          --vnavigatoroff
+          else
+            -- not possible but added for code coverage's sake
+          end if;
+          --vnavigatoron
+          case g_dout_w0x0f_v is
+            when g_t_klim_w0x0f  => g_t_klim_dout <= din(i*32+31 downto i*32);
+            when g_t_u_w0x0f =>
+              -- output klim
+              for j in 0 to 31 loop
+                if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then
+                  g_t_u_dout(j) <= din(32*i+j);
+                end if;
+              end loop;
+            when g_t_l_w0x0f               => g_t_l_dout                     <= din(i*32+31 downto i*32);
+            when g_t_hhh_l_w0x0f       => g_t_hhh_l_dout             <= din(i*32+31 downto i*32);
+            when g_t_jkl_sink_l_w0x0f    => g_t_jkl_sink_l_dout          <= din(i*32+31 downto i*32);
+            when g_secondary_t_l_w0x0f     => g_secondary_t_l_dout           <= din(i*32+31 downto i*32);
+            when g_style_c_l_w0x0f       => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32);
+            when g_e_z_w0x0f            => g_e_z_dout                  <= din(i*32+31 downto i*32);
+            when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout       <= din(i*32+31 downto i*32);
+            when g_style_vfr_w0x0f                => null;  -- read-only register
+            when g_style_klim_w0x0f                  => g_style_klim_dout                        <= din(i*32+31 downto i*32);
+            when g_unklimed_style_vfr_w0x0f       => null;  -- read-only register
+            when g_style_t_y_w0x0f       => g_style_t_y_dout             <= din(i*32+31 downto i*32);
+            when g_n_l_w0x0f            => g_n_l_dout                  <= din(i*32+31 downto i*32);
+            when g_n_vfr_w0x0f            => null;  -- writes
+            when g_e_n_r_w0x0f       => g_e_n_r_dout             <= din(i*32+31 downto i*32);
+            when g_n_r_bne_w0x0f       => g_n_r_bne_dout             <= din(i*32);
+            when g_n_div_rebeq_w0x0f    => g_n_div_rebeq_dout          <= din(i*32+31 downto i*32) or
+                                                                                                        g_n_div_rebeq_dout;  -- a '1' writes
+            when g_alu_l_w0x0f                => g_alu_l_dout                      <= din(i*32+31 downto i*32);
+            when g_t_qaz_mult_low_w0x0f     => g_t_qaz_mult_low_dout           <= din(i*32+31 downto i*32);
+            when g_t_qaz_mult_high_w0x0f    => g_t_qaz_mult_high_dout          <= din(i*32+31 downto i*32);
+            when gwerthernal_style_u_w0x0f        => gwerthernal_style_u_dout              <= din(i*32+31 downto i*32);
+            when gwerthernal_style_l_w0x0f       => gwerthernal_style_l_dout             <= din(i*32+31 downto i*32);
+            --vnavigatoroff                                                          
+            when others                                => null;
+            --vnavigatoron                                                        
+          end case;
+        end loop;
+
+      end if;
+    end if;
+  end process;
+
+  -- sample
+  g_zaq_in_sample_proc :
+  process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      q_g_zaq_in  <= (others => '0');
+      q2_g_zaq_in <= (others => '0');
+      q3_g_zaq_in <= (others => '0');
+    elsif( sysclk'event and sysclk = '1' ) then
+      q_g_zaq_in  <= g_zaq_in;
+      q2_g_zaq_in <= q_g_zaq_in;
+      q3_g_zaq_in <= g_zaq_in_y;
+    end if;
+  end process;
+
+  --  vfr register
+  g_unklimed_style_vfr_dout <= q2_g_zaq_in;
+
+  -- switch
+  g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in;
+
+  -- qaz
+  g_style_vfr_dout <=              -- top 2
+                           (g_zaq_in_y(31 downto 4) &
+                            --  FSM
+                            (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
+                             -- otherwise just use
+                             (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0))));
+  
+  -- in scan mode
+  g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1' 
+  --vnavigatoroff
+                                 else g_style_t_y_dout;
+  --vnavigatoron
+
+  g_sys_in_i                 <= (-- top 28
+                                 (g_zaq_in_y_no_dout(31 downto 4) &
+                                  --  is enabled
+                                  (( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
+                                   -- otherwise just use
+                                   (not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0)))));
+
+  g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout );
+
+  g_sys_in <= g_sys_in_ii;
+ 
+  lpq_proc :
+  process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      q_g_zaq_in_cd      <= (others => '0');
+      q_g_unzq          <= (others => '1');
+    elsif( sysclk'event and sysclk = '1' ) then
+      --  sample
+      if( debct_ping = '1') then
+        --  taken
+        for i in 0 to 3 loop
+          if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
+            q_g_unzq(i) <= '1';
+          else
+            if( q_g_unzq(i) = '0' ) then
+              q_g_zaq_in_cd(i) <= g_zaq_in_y(i);
+            else
+              q_g_unzq(i) <= '0';
+            end if;
+          end if;
+        end loop;
+      else
+        for i in 0 to 3 loop
+          if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
+            q_g_unzq(i) <= '1';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+  -- generate lqqs 
+  sample_forwerth_proc :
+  process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      q_g_style_vfr_dout <= (others => '0');
+    elsif( sysclk'event and sysclk = '1' ) then
+      if( scanb = '1' ) then
+        q_g_style_vfr_dout <= g_style_vfr_dout;
+      --vnavigatoroff
+      else
+        -- in scan 
+        q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii;
+      end if;
+      --vnavigatoron
+    end if;
+  end process;
+
+  -- generate
+  g_n_active <=  -- 1 to 0
+                            (((q_g_style_vfr_dout and not g_style_vfr_dout) or
+                             --  get this
+                             (not q_g_style_vfr_dout and g_style_vfr_dout and
+                              g_n_both_qbars_l_dout))) and
+                            -- must be 
+                             g_n_l_dout;
+  
+  -- check for lqq active and set lqq vfr register
+  -- also clear
+  n_proc :
+  process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      g_n_vfr_dout <= (others => '0');
+      gwerth                  <= (others => '0');
+    elsif( sysclk'event and sysclk = '1' ) then
+      for i in 0 to 31 loop
+        --  lqq
+        --  vfr  matches
+        if( g_n_active(i) = '1' ) then
+          gwerth(i) <= '1';
+          if( g_e_z_dout(i) = '1' ) then
+            --  lqq          
+            g_n_vfr_dout(i) <= '1';
+          else
+            g_n_vfr_dout(i) <= q_g_style_vfr_dout(i);
+          end if;
+        else
+          --  clear
+          if( g_e_z_dout(i) = '0' ) then
+	         g_n_vfr_dout(i) <= q_g_style_vfr_dout(i);  -- default always assign
+            -- in both
+            if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then
+              gwerth(i) <= '0';
+            end if;
+          else            
+            -- write
+            if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then
+              gwerth(i) <= '0';
+              g_n_vfr_dout(i) <= '0';
+            end if;
+          end if;
+        end if;
+      end loop;
+    end if;
+  end process;
+
+  ----
+  -- Create the Lqq
+  createwerth_vec_proc :
+  process( g_n_r_bne_dout, g_e_n_r_dout)
+    variable imod8, idiv8 : integer;
+  begin
+    for i in 0 to 31 loop
+      imod8 := i mod 8;
+      idiv8 := i / 8;
+
+      if( g_n_r_bne_dout = '0' ) then
+        -- non-unique
+        g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
+      else
+        -- unique
+        if( imod8 = 0 ) then
+          g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
+        else
+          g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) +
+                                                             to_unsigned(imod8, 8));
+        end if;
+      end if;
+    end loop;
+  end process;
+
+  ----
+  -- Qaz
+  g_noop <= g_n_div_rebeq_dout;
+
+  
+  create_g_ack_bne_proc :
+  process( swe_ed,swe_lv,g_e_z_dout)
+  begin
+    for i in 0 to 31 loop
+      if( g_e_z_dout(i) = '1') then
+        swe_qaz1(i) <= swe_ed;
+      else
+        swe_qaz1(i) <= swe_lv;
+      end if;
+    end loop;
+  end process;
+
+end rtl;
diff --git a/examples/clk.vhd b/examples/clk.vhd
new file mode 100644
index 0000000..81372d9
--- /dev/null
+++ b/examples/clk.vhd
@@ -0,0 +1,36 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
+                     ival : in std_logic_vector(31 downto 0)
+                     );
+end clk;
+architecture rtl of clk is
+  signal foo : std_logic_vector(10+3 downto 0);
+  signal baz : std_logic_vector(2 downto 0);
+  signal egg : std_logic_vector(4 to 7-1);
+begin
+  pfoo: process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      foo <= (others => '1');
+    elsif( sysclk'event and sysclk = '1' ) then
+      foo <= ival(31 downto 31-(10+3));
+    end if;
+  end process;
+  pbaz: process(preset, dsysclk)
+  begin
+    if( preset /= '1' ) then
+      baz <= (others => '0');
+    elsif( dsysclk'event and dsysclk = '0' ) then
+      baz <= ival(2 downto 0);
+    end if;
+  end process;
+  pegg: process(qreset, esysclk)
+  begin
+    if( qreset /= '1' ) then
+      egg <= (others => '0');
+    elsif( esysclk'event and esysclk = '0' ) then
+      egg <= ival(6 downto 4);
+    end if;
+  end process;
+end rtl;
diff --git a/examples/counters.vhd b/examples/counters.vhd
new file mode 100644
index 0000000..044a9c5
--- /dev/null
+++ b/examples/counters.vhd
@@ -0,0 +1,348 @@
+library IEEE;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counters is
+  port(
+    sysclk : in  std_logic;
+    foo_card : in  std_logic;
+    wfoo0_baz : in  std_logic;
+    wfoo0_blrb : in  std_logic;
+    wfoo0_zz1pb : in  std_logic;
+    wfoo0_turn : in  std_logic_vector(31 downto 0);
+    debct_baz : in  std_logic;
+    debct_blrb : in  std_logic;
+    debct_zz1pb : in  std_logic;
+    debct_bar : in  std_logic;
+    debct_turn : in  std_logic_vector(31 downto 0);
+    Z0_bar : in  std_logic;
+    Z0_baz : in  std_logic;
+    Z0_blrb : in  std_logic;
+    Z0_zz1pb : in  std_logic;
+    Z0_turn : in  std_logic_vector(31 downto 0);
+    Y1_bar : in  std_logic;
+    Y1_baz : in  std_logic;
+    Y1_blrb : in  std_logic;
+    Y1_zz1pb : in  std_logic;
+    Y1_turn : in  std_logic_vector(31 downto 0);
+    X2_bar : in  std_logic;
+    X2_baz : in  std_logic;
+    X2_blrb : in  std_logic;
+    X2_zz1pb : in  std_logic;
+    X2_turn : in  std_logic_vector(31 downto 0);
+    W3_bar : in  std_logic;
+    W3_baz : in  std_logic;
+    W3_blrb : in  std_logic;
+    W3_zz1pb : in  std_logic;
+    W3_turn : in  std_logic_vector(31 downto 0);
+    -- to engine block
+    Z0_cwm : out std_logic;
+    Z0 : out std_logic_vector(31 downto 0);
+    Y1_cwm : out std_logic;
+    Y1 : out std_logic_vector(31 downto 0);
+    X2_cwm : out std_logic;
+    X2 : out std_logic_vector(31 downto 0);
+    W3_cwm : out std_logic;
+    W3 : out std_logic_vector(31 downto 0);
+    wfoo0_cwm : out std_logic;
+    wfoo0_llwln : out std_logic_vector(31 downto 0);
+    debct_cwm : out std_logic;
+    debct_pull : out std_logic;
+    debct : out std_logic_vector(31 downto 0);
+    wdfilecardA2P : out std_logic
+    );
+end counters;
+
+
+architecture rtl of counters is
+
+  signal wfoo0_llwln_var : unsigned(31 downto 0);
+  signal debct_var : unsigned(31 downto 0);
+  signal Z0_var : unsigned(31 downto 0);
+  signal Y1_var : unsigned(31 downto 0);
+  signal X2_var : unsigned(31 downto 0);
+  signal W3_var : unsigned(31 downto 0);
+  signal main_wfoo0_cwm : std_logic;
+  signal do_q3p_Z0 : std_logic;
+  signal do_q3p_Y1 : std_logic;
+  signal do_q3p_X2 : std_logic;
+  signal do_q3p_W3 : std_logic;
+  signal do_q3p_wfoo0 : std_logic;
+  signal do_q3p_debct : std_logic;
+
+  signal Z0_cwm_i : std_logic;
+  signal Y1_cwm_i : std_logic;
+  signal X2_cwm_i : std_logic;
+  signal W3_cwm_i : std_logic;
+  signal debct_cwm_i : std_logic;
+
+  signal file_card_i : std_logic;
+  signal do_file_card_i : std_logic;
+  signal prev_do_file_card : std_logic;
+
+
+begin
+
+  -----
+  -- form the outputs
+  wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var);
+  debct       <= std_logic_vector(debct_var);
+  Z0         <= std_logic_vector(Z0_var);
+  Y1         <= std_logic_vector(Y1_var);
+  X2         <= std_logic_vector(X2_var);
+  W3         <= std_logic_vector(W3_var);
+  Z0_cwm     <= Z0_cwm_i;
+  Y1_cwm     <= Y1_cwm_i;
+  X2_cwm     <= X2_cwm_i;
+  W3_cwm     <= W3_cwm_i;
+  debct_cwm   <= debct_cwm_i;
+
+  wdfilecardA2P <= do_file_card_i;
+
+  LLWLNS :
+  process(foo_card, sysclk)
+  begin
+    if foo_card = '1' then
+      wfoo0_llwln_var <= (others => '0');
+      debct_var       <= (others => '0');
+      Z0_var         <= (others => '0');
+      Y1_var         <= (others => '0');
+      X2_var         <= (others => '0');
+      W3_var         <= (others => '0');
+
+      wfoo0_cwm       <= '0';
+      debct_cwm_i     <= '0';
+      debct_pull     <= '0';
+      Z0_cwm_i       <= '0';
+      Y1_cwm_i       <= '0';
+      X2_cwm_i       <= '0';
+      W3_cwm_i       <= '0';
+      main_wfoo0_cwm <= '0';
+      file_card_i    <= '0';
+
+      do_q3p_wfoo0     <= '0';
+      do_file_card_i    <= '0';
+      prev_do_file_card <= '0';
+
+      do_q3p_Z0 <= '0';
+      do_q3p_Y1 <= '0';
+      do_q3p_X2 <= '0';
+      do_q3p_W3 <= '0';
+      do_q3p_debct <= '0';
+
+    else
+      if sysclk'event and sysclk = '1' then
+
+        -- pull
+        debct_pull     <= '0';
+        do_file_card_i <= '0';
+
+        ----
+        --  wfoo0
+
+        if wfoo0_baz = '1' then
+          wfoo0_llwln_var <= unsigned(wfoo0_turn);
+          main_wfoo0_cwm <= '0';
+          if wfoo0_llwln_var = "00000000000000000000000000000000" then
+            do_q3p_wfoo0  <= '0';
+          else
+            do_q3p_wfoo0  <= '1';
+          end if;
+        else
+          if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then
+            wfoo0_llwln_var <= wfoo0_llwln_var - 1;
+            if (wfoo0_llwln_var = "00000000000000000000000000000000") then
+              wfoo0_llwln_var <= unsigned(wfoo0_turn);
+              if main_wfoo0_cwm = '0' then
+                wfoo0_cwm <= '1';
+                main_wfoo0_cwm <= '1';
+              else
+                do_file_card_i <= '1';
+                do_q3p_wfoo0 <= '0';
+              end if;
+            end if;
+          end if;
+        end if;
+
+        if wfoo0_zz1pb = '0' then
+          wfoo0_cwm <= '0';
+        end if;
+
+        if Z0_baz = '1' then                                       -- counter Baz
+          Z0_var <= unsigned(Z0_turn);
+          if Z0_turn = "00000000000000000000000000000000" then
+            do_q3p_Z0 <= '0';
+          else
+            do_q3p_Z0 <= '1';
+          end if;
+        else
+          if do_q3p_Z0 = '1' and Z0_blrb = '1' then
+            if Z0_bar = '0' then
+              if Z0_cwm_i = '0' then
+                if do_q3p_Z0 = '1' then
+                  Z0_var <= Z0_var - 1;
+                  if (Z0_var = "00000000000000000000000000000001") then
+                    Z0_cwm_i    <= '1';
+                    do_q3p_Z0 <= '0';
+                  end if;
+                end if;
+              end if;
+            else
+              Z0_var <= Z0_var - 1;
+              if (Z0_var = "00000000000000000000000000000000") then
+                Z0_cwm_i <= '1';
+                Z0_var   <= unsigned(Z0_turn);
+              end if;
+            end if;  -- Z0_bar
+          end if;
+        end if;  -- Z0_blrb
+
+        if Z0_zz1pb = '0' then
+          Z0_cwm_i <= '0';
+        end if;
+
+        if Y1_baz = '1' then                                       -- counter Baz
+          Y1_var <= unsigned(Y1_turn);
+          if Y1_turn = "00000000000000000000000000000000" then
+            do_q3p_Y1 <= '0';
+          else
+            do_q3p_Y1 <= '1';
+          end if;
+        elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then
+          if Y1_bar = '0' then
+            if Y1_cwm_i = '0' then
+              if do_q3p_Y1 = '1' then
+                Y1_var <= Y1_var - 1;
+                if (Y1_var = "00000000000000000000000000000001") then
+                  Y1_cwm_i    <= '1';
+                  do_q3p_Y1 <= '0';
+                end if;
+              end if;
+            end if;
+          else
+            Y1_var <= Y1_var - 1;
+
+            if (Y1_var = "00000000000000000000000000000000") then
+              Y1_cwm_i <= '1';
+              Y1_var   <= unsigned(Y1_turn);
+            end if;
+          end if;  -- Y1_bar
+
+        end if;  -- Y1_blrb
+
+        if Y1_zz1pb = '0' then
+          Y1_cwm_i <= '0';
+        end if;
+
+        if X2_baz = '1' then                                       -- counter Baz
+          X2_var <= unsigned(X2_turn);
+          if X2_turn = "00000000000000000000000000000000" then
+            do_q3p_X2 <= '0';
+          else
+            do_q3p_X2 <= '1';
+          end if;
+        elsif do_q3p_X2 = '1' and X2_blrb = '1' then
+          if X2_bar = '0' then
+            if X2_cwm_i = '0' then
+		        if do_q3p_X2 = '1' then
+	   	        X2_var <= X2_var - 1;
+	      	     if (X2_var = "00000000000000000000000000000001") then
+   	             X2_cwm_i    <= '1';
+	                do_q3p_X2 <= '0';
+                 end if;
+              end if;
+            end if;
+          else
+            X2_var <= X2_var - 1;
+
+            if (X2_var = "00000000000000000000000000000000") then  --{
+              X2_cwm_i <= '1';
+              X2_var   <= unsigned(X2_turn);
+            end if;
+          end if;  --X2_bar
+        end if;  -- X2_blrb
+
+        if X2_zz1pb = '0' then
+          X2_cwm_i <= '0';
+        end if;
+
+
+        if W3_baz = '1' then                                       -- counter Baz
+          W3_var <= unsigned(W3_turn);
+          if W3_turn = "00000000000000000000000000000000" then
+            do_q3p_W3 <= '0';
+          else
+            do_q3p_W3 <= '1';
+          end if;
+        elsif do_q3p_W3 = '1' and W3_blrb = '1' then
+          if W3_bar = '0' then
+            if W3_cwm_i = '0'then
+              if do_q3p_W3 = '1' then
+                W3_var <= W3_var - 1;
+                if (W3_var = "00000000000000000000000000000001") then
+                  W3_cwm_i    <= '1';
+                  do_q3p_W3 <= '0';
+                end if;
+              end if;
+            end if;
+          else
+            W3_var <= W3_var - 1;
+
+            if (W3_var = "00000000000000000000000000000000") then  --{
+              W3_cwm_i <= '1';
+              W3_var   <= unsigned(W3_turn);
+            end if;
+          end if;  -- W3_bar
+
+        end if;  -- W3_blrb
+
+        if W3_zz1pb = '0' then
+          W3_cwm_i <= '0';
+        end if;
+
+        if debct_baz = '1' then                                       -- counter Baz
+          debct_var <= unsigned(debct_turn);
+          if debct_turn = "00000000000000000000000000000000" then
+            do_q3p_debct <= '0';
+          else
+            do_q3p_debct <= '1';
+          end if;
+        elsif do_q3p_debct = '1' and debct_blrb = '1' then
+          if debct_bar = '0' then
+            if debct_cwm_i = '0'then
+              if do_q3p_debct = '1' then
+                debct_var <= debct_var - 1;
+                if (debct_var = "00000000000000000000000000000001") then
+                  debct_cwm_i    <= '1';
+                  debct_pull    <= '1';
+                  do_q3p_debct <= '0';
+                end if;
+              end if;
+            end if;
+          else
+            ---- T
+            --  Continue
+            debct_var <= debct_var - 1;
+
+            -- ending
+            if (debct_var = "00000000000000000000000000000000") then  --{
+              debct_cwm_i <= '1';
+              debct_pull    <= '1';
+              debct_var   <= unsigned(debct_turn);
+            end if;
+          end if;  -- debct_bar
+
+        end if;  -- debct_blrb
+
+
+        -- comment
+        if debct_zz1pb = '0' then
+          debct_cwm_i <= '0';
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+end rtl;
diff --git a/examples/expr.vhd b/examples/expr.vhd
new file mode 100644
index 0000000..24b3885
--- /dev/null
+++ b/examples/expr.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+entity expr is port( reset, sysclk, ival : in std_logic);
+end expr;
+architecture rtl of expr is
+  signal foo : std_logic_vector(13 downto 0);
+  signal baz : std_logic_vector(2 downto 0);
+  signal bam : std_logic_vector(22 downto 0);
+  signal out_i : std_logic_vector(5 downto 3);
+  signal input_status : std_logic_vector(8 downto 0);
+  signal enable, debug, aux, outy, dv, value : std_logic;
+begin
+  -- drive input status
+  input_status <=    -- top bits
+                           (foo(9 downto 4) &
+                            (( baz(3 downto 0) and foo(3 downto 0) or
+                             (not baz(3 downto 0) and bam(3 downto 0)))));
+  -- drive based on foo
+  out_i <=
+    -- if secondary enabl is set then drive aux out
+    (enable and (aux xor outy)) or
+    -- if debug is enabled               
+    (debug and dv and not enable) or
+    -- otherwise we drive reg
+    (not debug and not enable and value);
+  -- not drive
+
+  pfoo: process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      foo <= (others => '0');
+    elsif( sysclk'event and sysclk = '0' ) then
+      foo(3*(2-1)) <= (4*(1+2));
+      bam(foo'range) <= foo;
+    end if;
+  end process;
+end rtl;
diff --git a/examples/for.vhd b/examples/for.vhd
new file mode 100644
index 0000000..796f209
--- /dev/null
+++ b/examples/for.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+entity forp is port(
+  reset, sysclk : in std_logic
+);
+end forp;
+architecture rtl of forp is
+
+  signal selection : std_logic;
+  signal egg_timer : std_logic_vector(6 downto 0);
+begin
+  TIMERS :
+  process(reset, sysclk)
+    variable timer_var : integer:= 0;
+    variable a, i, j, k : integer;
+    variable zz5 : std_logic_vector(31 downto 0);
+    variable zz : std_logic_vector(511 downto 0);
+  begin
+    if reset = '1' then
+      selection <= '1';
+      timer_var := 2;
+      egg_timer <= (others => '0');
+    elsif sysclk'event and sysclk = '1' then
+      --  pulse only lasts for once cycle
+      selection <= '0';
+      egg_timer <= (others => '1');
+      for i in 0 to j*k loop
+        a := a + i;
+        for k in a-9 downto -14 loop
+          zz5 := zz(31+k downto k);
+        end loop;  -- k
+      end loop;  -- i
+    end if;
+  end process;
+
+end rtl;
diff --git a/examples/generate.vhd b/examples/generate.vhd
new file mode 100644
index 0000000..56d5d3c
--- /dev/null
+++ b/examples/generate.vhd
@@ -0,0 +1,50 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+entity gen is   generic(
+  bus_width : integer := 15;
+  TOP_GP2 : integer:= 0
+  );
+                port(
+                  sysclk, reset, wrb : in std_logic;
+                  din : in std_logic_vector(bus_width downto 0);
+                  rdout: out std_logic_vector(bus_width downto 0)
+                  
+);
+end gen;
+architecture rtl of gen is
+  component wbit1                       -- register bit default 1
+    port(
+      clk   : in  std_logic;
+      wrb   : in  std_logic;
+      reset : in  std_logic;
+      enb   : in  std_logic;
+      din   : in  std_logic;
+      dout  : out std_logic);
+  end component;
+
+  signal regSelect : std_logic_vector(bus_width * 2 downto 0);
+begin
+  -----------------------------------------------------
+  -- Reg    : GP 2
+  -- Active : 32
+  -- Type   : RW
+  -----------------------------------------------------
+  reg_gp2 : for bitnum in 0 to bus_width generate
+    wbit1_inst : wbit1
+      PORT MAP(
+      clk   => sysclk,
+      wrb   => wrb,
+      reset => reset,
+      enb   => regSelect(TOP_GP2),
+      din   => din(bitnum),
+      dout  => rdout(bitnum)
+      );
+  end generate;
+
+  process(sysclk) begin
+    if sysclk'event and sysclk = '1' then
+      regSelect(1) <= '1';
+    end if;
+  end process;
+
+end rtl;
diff --git a/examples/generic.vhd b/examples/generic.vhd
new file mode 100644
index 0000000..6ffc208
--- /dev/null
+++ b/examples/generic.vhd
@@ -0,0 +1,32 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+entity test is
+  generic(
+    dog_width : std_logic_vector(7 downto 0) := "10101100";
+    bus_width : integer := 32
+    );
+    port( reset, sysclk : in std_logic;
+          a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0)
+          );
+end test;
+architecture rtl of test is
+  signal foo : std_logic_vector(1+1 downto 0);
+  signal code,code1: std_logic_vector(9 downto 0);
+  signal egg : std_logic_vector(324 to 401);
+  signal baz : std_logic_vector(bus_width*3-1 to bus_width*4);
+  signal complex : std_logic_vector(31 downto 0);
+begin
+  -- Example of with statement
+  with foo(2 downto 0) select
+    code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110",
+                        "11100010" when "101",
+                        (others => '1') when "010",
+                        (others => '0') when "011",
+                        a + b + '1' when others;
+  code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
+  
+  foo <= (others => '0');
+  egg <= (others => '0');
+  baz <= (others => '1');
+  complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001";
+end rtl;
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
new file mode 100644
index 0000000..0ddd610
--- /dev/null
+++ b/examples/genericmap.vhd
@@ -0,0 +1,79 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+entity test is
+generic(
+  rst_val   : std_logic := '0';
+  thing_size: integer := 201;
+  bus_width : integer := 201 mod 32);
+port(
+  clk, rstn : in std_logic;
+  en, start_dec : in std_logic;
+  addr : in std_logic_vector(2 downto 0);
+  din : in std_logic_vector(25 downto 0);
+  we : in std_logic;
+  pixel_in : in std_logic_vector(7 downto 0);
+  pix_req : in std_logic;
+  config, bip : in std_logic;
+  a, b : in std_logic_vector(7 downto 0);
+  c, load : in std_logic_vector(7 downto 0);
+  pack : in std_logic_vector(6 downto 0);
+  base : in std_logic_vector(2 downto 0);
+  qtd : in std_logic_vector(21 downto 0);
+  -- Outputs
+  dout : out std_logic_vector(25 downto 0);
+  pixel_out : out std_logic_vector(7 downto 0);
+  pixel_valid : out std_logic;
+  code : out std_logic_vector(9 downto 0);
+  complex : out std_logic_vector(23 downto 0);
+  eno : out std_logic
+);
+end test;
+architecture rtl of test is
+
+  component dsp
+    generic(
+      rst_val   : std_logic := '0';
+      thing_size: integer := 201;
+      bus_width : integer := 22);
+    port(
+      -- Inputs
+      clk, rstn : in std_logic;
+      -- Outputs
+      dout : out std_logic_vector(bus_width downto 0);
+      memaddr : out std_logic_vector(5 downto 0);
+      memdout : out std_logic_vector(13 downto 0)
+      );
+  end component;
+  signal param : std_logic_vector(7 downto 0);
+  signal selection : std_logic;
+  signal start, enf : std_logic; -- Start and enable signals
+  signal memdin : std_logic_vector(13 downto 0);
+  signal memaddr : std_logic_vector(5 downto 0);
+  signal memdout : std_logic_vector(13 downto 0);
+  signal colour : std_logic_vector(1 downto 0);
+begin
+  dsp_inst0 : dsp
+    port map(
+    -- Inputs
+    clk => clk,
+    rstn => rstn,
+    -- Outputs
+    dout => dout,
+    memaddr => memaddr,
+    memdout => memdout
+  );
+
+  dsp_inst1 : dsp
+    generic map(
+      rst_val   => '1',
+      bus_width => 16)
+    port map(
+    -- Inputs
+    clk => clk,
+    rstn => rstn,
+    -- Outputs
+    dout => dout,
+    memaddr => memaddr,
+    memdout => memdout
+  );
+end rtl;
diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd
new file mode 100644
index 0000000..161ba34
--- /dev/null
+++ b/examples/ifchain.vhd
@@ -0,0 +1,20 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+entity test is port(
+  clk, rstn : in std_logic
+);
+end test;
+architecture rtl of test is
+  signal a : std_logic_vector(3 downto 0);
+  signal b : std_logic_vector(3 downto 0);
+  signal status : std_logic;
+begin
+  process(clk) begin
+    if clk'event and clk = '1' then
+      if  b(1) & a(3 downto 2)  = "001" then
+        status <= "1";
+      end if;          
+    end if;
+  end process;
+
+end rtl;
diff --git a/examples/test.vhd b/examples/test.vhd
new file mode 100644
index 0000000..0532a7b
--- /dev/null
+++ b/examples/test.vhd
@@ -0,0 +1,191 @@
+-- Project: VHDL to Verilog RTL translation 
+-- Revision: 1.0 
+-- Date of last Revision: February 27 2001 
+-- Designer: Vincenzo Liguori 
+-- vhd2vl test file
+-- This VHDL file exercises vhd2vl
+
+LIBRARY IEEE;
+
+USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+
+entity test is port(
+  -- Inputs
+  clk, rstn : in std_logic;
+  en, start_dec : in std_logic;
+  addr : in std_logic_vector(2 downto 0);
+  din : in std_logic_vector(25 downto 0);
+  we : in std_logic;
+  pixel_in : in std_logic_vector(7 downto 0);
+  pix_req : in std_logic;
+  config, bip : in std_logic;
+  a, b : in std_logic_vector(7 downto 0);
+  c, load : in std_logic_vector(7 downto 0);
+  pack : in std_logic_vector(6 downto 0);
+  base : in std_logic_vector(2 downto 0);
+  qtd : in std_logic_vector(21 downto 0);
+  -- Outputs
+  dout : out std_logic_vector(25 downto 0);
+  pixel_out : out std_logic_vector(7 downto 0);
+  pixel_valid : out std_logic;
+  code : out std_logic_vector(9 downto 0);
+  code1 : out std_logic_vector(9 downto 0);
+  complex : out std_logic_vector(23 downto 0);
+  eno : out std_logic
+);  
+end test;
+
+architecture rtl of test is
+
+-- Components declarations are ignored by vhd2vl
+-- but they are still parsed
+
+component dsp port(
+  -- Inputs
+  clk, rstn : in std_logic;
+  en, start : in std_logic;
+  param : in std_logic_vector(7 downto 0);
+  addr : in std_logic_vector(2 downto 0);
+  din : in std_logic_vector(25 downto 0);
+  we : in std_logic;
+  memdin : out std_logic_vector(13 downto 0);
+    -- Outputs
+  dout : out std_logic_vector(25 downto 0);
+  memaddr : out std_logic_vector(5 downto 0);
+  memdout : out std_logic_vector(13 downto 0)
+);
+end component;
+
+component mem port(
+  -- Inputs
+  clk, rstn : in std_logic;
+  en : in std_logic;
+  cs : in std_logic;
+  addr : in std_logic_vector(5 downto 0);
+  din : in std_logic_vector(13 downto 0);
+  -- Outputs
+  dout : out std_logic_vector(13 downto 0)
+);
+end component;  
+
+  type state is (red, green, blue, yellow);
+  signal status : state;
+  constant PARAM1 : std_logic_vector(7 downto 0):="01101101";
+  constant PARAM2 : std_logic_vector(7 downto 0):="11001101";
+  constant PARAM3 : std_logic_vector(7 downto 0):="00010111";
+  signal param : std_logic_vector(7 downto 0);
+  signal selection : std_logic;
+  signal start, enf : std_logic; -- Start and enable signals
+  signal memdin : std_logic_vector(13 downto 0);
+  signal memaddr : std_logic_vector(5 downto 0);
+  signal memdout : std_logic_vector(13 downto 0);
+  signal colour : std_logic_vector(1 downto 0);
+begin
+
+  param <= PARAM1 when config = '1' else PARAM2 when status = green else PARAM3;
+
+  -- Synchronously process
+  process(clk) begin
+    if clk'event and clk = '1' then 
+      pixel_out <= pixel_in xor "11001100";
+    end if;
+  end process;
+
+  -- Synchronous process
+  process(clk) begin
+    if rising_edge(clk) then 
+      case status is
+        when red => colour <= "00";
+        when green => colour <= "01";
+        when blue => colour <= "10";
+        when others => colour <= "11";
+      end case;
+    end if;
+  end process;
+
+  -- Synchronous process with asynch reset
+  process(clk,rstn) begin
+    if rstn = '0' then
+      status <= red;
+    elsif rising_edge(clk) then 
+      case status is
+        when red => 
+          if pix_req = '1' then
+            status <= green;
+          end if;
+        when green =>
+          if a(3) = '1' then
+            start <= start_dec;
+            status <= blue;
+          elsif (b(5) & a(3 downto 2)) = "001" then
+            status <= yellow;
+          end if;          
+        when blue =>
+          status <= yellow;
+        when others =>
+          start <= '0';
+          status <= red;
+      end case;
+    end if;
+  end process;
+
+  -- Example of with statement
+  with memaddr(2 downto 0) select
+    code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110",
+                        "11100010" when "101",
+                        (others => '1') when "010",
+                        (others => '0') when "011",
+                        a + b + '1' when others;
+  code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
+  
+  -- Asynch process
+  decode : process(we, addr, config, bip) begin
+    if we = '1' then
+      if addr(2 downto 0) = "100" then
+        selection <= '1';
+      elsif (b & a) = a & b and bip = '0' then
+        selection <= config;
+      else
+        selection <= '1';
+      end if;
+    else
+      selection <= '0';
+    end if;
+  end process decode;
+
+  -- Components instantiation
+  dsp_inst : dsp port map(
+    -- Inputs
+    clk => clk,
+    rstn => rstn,
+    en => en,
+    start => start,
+    param => param,
+    addr => addr,
+    din => din,
+    we => we,
+    memdin => memdin,
+    -- Outputs
+    dout => dout,
+    memaddr => memaddr,
+    memdout => memdout
+  );
+  
+  dsp_mem : mem port map(
+    -- Inputs
+    clk => clk,
+    rstn => rstn,
+    en => en,
+    cs => selection,
+    addr => memaddr,
+    din => memdout,
+    -- Outputs
+    dout => memdin
+  );
+
+  complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001";
+
+  enf <= '1' when a = "1101111" + load and c < "1000111" else '0';
+  eno <= enf;
+
+end rtl;