Fixes in examples and translated examples to avoid some complains of iVerilog

'test' was repeated as entity/module name
'config' was used as port name and is a reserved word in Verilog.

4 files changed, 14 insertions, 14 deletions

diff --git a/examples/generic.vhd b/examples/generic.vhd
index e3b6801..8a12b50 100644
--- a/examples/generic.vhd
+++ b/examples/generic.vhd
@@ -1,7 +1,7 @@
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
 
-entity test is
+entity generic1 is
   generic(
     dog_width : std_logic_vector(7 downto 0) := "10101100";
     bus_width : integer := 32
@@ -9,8 +9,8 @@ entity test is
     port( reset, sysclk : in std_logic;
           a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0)
           );
-end test;
-architecture rtl of test is
+end generic1;
+architecture rtl of generic1 is
   signal foo : std_logic_vector(1+1 downto 0);
   signal code,code1: std_logic_vector(9 downto 0);
   signal egg : std_logic_vector(324 to 401);
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 1132554..33d9363 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -1,6 +1,6 @@
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
-entity test is
+entity genericmap is
 generic(
   rst_val   : std_logic := '0';
   thing_size: integer := 201;
@@ -13,7 +13,7 @@ port(
   we : in std_logic;
   pixel_in : in std_logic_vector(7 downto 0);
   pix_req : in std_logic;
-  config, bip : in std_logic;
+  bip : in std_logic;
   a, b : in std_logic_vector(7 downto 0);
   c, load : in std_logic_vector(7 downto 0);
   pack : in std_logic_vector(6 downto 0);
@@ -27,8 +27,8 @@ port(
   complex : out std_logic_vector(23 downto 0);
   eno : out std_logic
 );
-end test;
-architecture rtl of test is
+end genericmap;
+architecture rtl of genericmap is
 
   component dsp
     generic(
diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd
index dbc0a98..a830272 100644
--- a/examples/ifchain.vhd
+++ b/examples/ifchain.vhd
@@ -1,12 +1,12 @@
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
 
-entity test is port(
+entity ifchain is port(
   clk, rstn : in std_logic
 );
-end test;
+end ifchain;
 
-architecture rtl of test is
+architecture rtl of ifchain is
   type   t is array (3 downto 0) of std_logic_vector(31 downto 0);
   signal a : std_logic_vector(3 downto 0);
   signal b : std_logic_vector(3 downto 0);
diff --git a/examples/test.vhd b/examples/test.vhd
index bcc2968..b273e8f 100644
--- a/examples/test.vhd
+++ b/examples/test.vhd
@@ -18,7 +18,7 @@ entity test is port(
   we : in std_logic;
   pixel_in : in std_logic_vector(7 downto 0);
   pix_req : in std_logic;
-  config, bip : in std_logic;
+  config1, bip : in std_logic;
   a, b : in std_logic_vector(7 downto 0);
   c, load : in std_logic_vector(7 downto 0);
   pack : in std_logic_vector(6 downto 0);
@@ -82,7 +82,7 @@ end component;
   signal colour : std_logic_vector(1 downto 0);
 begin
 
-  param <= PARAM1 when config = '1' else PARAM2 when status = green else PARAM3;
+  param <= PARAM1 when config1 = '1' else PARAM2 when status = green else PARAM3;
 
   -- Synchronously process
   process(clk) begin
@@ -139,12 +139,12 @@ begin
   code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
   
   -- Asynch process
-  decode : process(we, addr, config, bip) begin
+  decode : process(we, addr, config1, bip) begin
     if we = '1' then
       if addr(2 downto 0) = "100" then
         selection <= '1';
       elsif (b & a) = a & b and bip = '0' then
-        selection <= config;
+        selection <= config1;
       else
         selection <= '1';
       end if;