New make target: verilogcheck

Requires iverilog to operate.
Scans resulting files in translated_examples directory.
This patch includes some simple fixes to reduce the number of errors reported,
but there are more that need further investigation.

2 files changed, 23 insertions, 0 deletions

diff --git a/examples/ifchain2.vhd b/examples/ifchain2.vhd
index 09794b1..e179960 100644
--- a/examples/ifchain2.vhd
+++ b/examples/ifchain2.vhd
@@ -3,12 +3,14 @@ USE IEEE.std_logic_1164.all;
 
 entity ifchain is port(
   clk, rstn : in std_logic;
+  enable: in std_logic;
   result: out std_logic
 );
 end ifchain;
 
 architecture rtl of ifchain is
   signal counter : std_logic_vector(3 downto 0);
+  constant CLK_DIV_VAL : unsigned(3 downto 0) := 11;
 begin
 
 clk_src : process(clk, rstn) is
diff --git a/examples/wbit1.vhd b/examples/wbit1.vhd
new file mode 100644
index 0000000..12b1e38
--- /dev/null
+++ b/examples/wbit1.vhd
@@ -0,0 +1,21 @@
+-- Nearly useless stub, it's here to support generate.vhd
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+
+entity wbit1 is
+    port(
+      clk   : in  std_logic;
+      wrb   : in  std_logic;
+      reset : in  std_logic;
+      enb   : in  std_logic;
+      din   : in  std_logic;
+      dout  : out std_logic);
+end;
+
+architecture rtl of wbit1 is
+    signal foo : std_logic;
+begin
+    process(clk) begin
+       dout <= '1';
+    end process;
+end rtl;