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* | Improve c89 compatibilityLarry Doolittle2017-11-211-9/+9
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* Add development hook for visualising slistsLarry Doolittle2017-11-201-0/+48
* Adding support for while loopLarry Doolittle2017-11-204-1/+69
* Align the prototypes for dsp in dsp and genericmapLarry Doolittle2017-11-202-4/+3
* Beginning support for assertionsLarry Doolittle2017-11-183-0/+26
* Simple fix to genericmap exampleLarry Doolittle2017-11-182-4/+4
* Fix capitalization of iverilogLarry Doolittle2017-11-171-1/+1
* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-173-15/+28
* Removed extra parentheses when parentheses are usedRodrigo Alejandro Melo2017-11-173-3/+4
* Removed unuseful parenthesesRodrigo Alejandro Melo2017-11-179-40/+40
* Fixed rebuild of vhd2vl in the main MakefileRodrigo Alejandro Melo2017-11-171-7/+4
* Used addnest function to replace code for BITVECTRodrigo Alejandro Melo2017-11-171-9/+2
* Parentheses were removed for CONVFUNC_1 (ex. to_integer)Rodrigo Alejandro Melo2017-11-172-4/+4
* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-163-4/+9
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-163-7/+26
* The resulting files of the GHDL analysis were moved to temp/vhdlRodrigo Alejandro Melo2017-11-161-2/+5
* Added the special file examples/todo.vhdRodrigo Alejandro Melo2017-11-162-2/+25
* Changes on translated_examples (dsp and ifchain2) due to previous changes in ...Rodrigo Alejandro Melo2017-11-162-2/+2
* Examples were corrected according to GHDL complainsRodrigo Alejandro Melo2017-11-165-8/+10
* Updates to CHANGELOG.mdLarry Doolittle2017-11-131-1/+17
* Squelch some trailing whitespaceLarry Doolittle2017-11-125-21/+20
* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-109-12/+178
* New make target: verilogcheckLarry Doolittle2017-11-105-0/+52
* New rem before END PROCESSLarry Doolittle2017-11-103-5/+73
* Experiment with OTHERS logicLarry Doolittle2017-11-093-14/+44
* Makefile adjustmentsLarry Doolittle2017-11-091-3/+8
* use enum for slist typeLarry Doolittle2017-11-092-22/+33
* one more rem in generic patternLarry Doolittle2017-11-091-4/+4
* Merge branch 'rodrigomelo9-master'Larry Doolittle2017-11-0934-1139/+700
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| * Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-198-22/+21
| * Improved WARNING messages indicationRodrigo Alejandro Melo2017-02-191-18/+14
| * Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-193-6/+7
| * Fixed warnig in vhd2vl.y introduced in the previous commitRodrigo Alejandro Melo2017-02-171-9/+7
| * Modified to use ',' to separate sensitivity list in verilog 2001Rodrigo Alejandro Melo2017-02-178-22/+31
| * Changed translated_examples due that Verilog 2001 is now the defaultRodrigo Alejandro Melo2017-02-1713-455/+162
| * Updated version and how to use in README.mdRodrigo Alejandro Melo2017-02-171-44/+41
| * Changed vhd2vl version to 3.0Rodrigo Alejandro Melo2017-02-171-2/+4
| * Changed default Verilog version to 2001Rodrigo Alejandro Melo2017-02-171-19/+13
| * Added command line option --quietRodrigo Alejandro Melo2017-02-1715-283/+14
| * New command line parsing using getoptRodrigo Alejandro Melo2017-02-162-29/+52
| * File names changed to be more GitHub friendlyRodrigo Alejandro Melo2017-02-163-0/+0
| * Added analysis of examples with GHDLRodrigo Alejandro Melo2017-02-1420-48/+57
| * Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-095-1/+71
| * Space deleted in the <size>'<radix><number> notationRodrigo Alejandro Melo2017-02-0914-250/+252
| * Added a Makefile for regression testingRodrigo Alejandro Melo2017-02-092-0/+23
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* vhd2vl-2.5Larry Doolittle2015-09-2017-50/+73
* vhd2vl-2.4Larry Doolittle2015-09-2019-190/+509
* vhd2vl-2.3Larry Doolittle2015-09-2019-145/+667
* vhd2vl-2.2Larry Doolittle2015-09-2029-0/+5949
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