Added analysis of examples with GHDL

Some examples were corrected according GHDL complains.
Corresponding traslated_examples were modified.
Use of synopsys libraries was removed.
Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned').
The problem was comented.

20 files changed, 57 insertions, 48 deletions

diff --git a/.gitignore b/.gitignore
index c8dd9c9..59b429a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,3 +5,6 @@ src/*.c
 src/*.h
 src/*.output
 src/vhd2vl
+
+examples/*.o
+examples/*.cf
diff --git a/Makefile b/Makefile
index dadb49d..5ffd313 100644
--- a/Makefile
+++ b/Makefile
@@ -11,11 +11,13 @@ src/vhd2vl:
 
 translate: src/vhd2vl
 	@mkdir -p temp/verilog
-	@$(foreach VHDL,$(VHDLS),cd examples; ../src/vhd2vl $(VHDL) ../temp/verilog/$(basename $(VHDL)).v)
+	#@make -C examples
+	@$(foreach VHDL,$(VHDLS),cd examples; echo "Translating: $(VHDL)";../src/vhd2vl $(VHDL) ../temp/verilog/$(basename $(VHDL)).v)
 
 diff: translate
 	@diff -u translated_examples temp/verilog
 
 clean:
 	make -C src clean
+	@make -C examples clean
 	rm -fr temp
diff --git a/examples/Makefile b/examples/Makefile
new file mode 100644
index 0000000..529668b
--- /dev/null
+++ b/examples/Makefile
@@ -0,0 +1,8 @@
+#!/usr/bin/make
+# by RAM 2017
+
+all:
+	ghdl -a *.vhd
+
+clean:
+	rm -fr *.o *.cf
diff --git a/examples/based.vhd b/examples/based.vhd
index d9b5a29..9ac5af9 100644
--- a/examples/based.vhd
+++ b/examples/based.vhd
@@ -1,5 +1,5 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all;
 
 entity based is port( sysclk : in std_logic);
 end based;
diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
index 9d76855..3fc1d9d 100644
--- a/examples/bigfile.vhd
+++ b/examples/bigfile.vhd
@@ -1,6 +1,5 @@
 library IEEE;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
 use ieee.numeric_std.all;
 
 -- CONNECTIVITY DEFINITION
diff --git a/examples/clk.vhd b/examples/clk.vhd
index 81372d9..541c7cd 100644
--- a/examples/clk.vhd
+++ b/examples/clk.vhd
@@ -1,5 +1,5 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all;
 entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
                      ival : in std_logic_vector(31 downto 0)
                      );
diff --git a/examples/counters.vhd b/examples/counters.vhd
index 044a9c5..77f7bbb 100644
--- a/examples/counters.vhd
+++ b/examples/counters.vhd
@@ -54,7 +54,6 @@ entity counters is
     );
 end counters;
 
-
 architecture rtl of counters is
 
   signal wfoo0_llwln_var : unsigned(31 downto 0);
@@ -81,7 +80,6 @@ architecture rtl of counters is
   signal do_file_card_i : std_logic;
   signal prev_do_file_card : std_logic;
 
-
 begin
 
   -----
@@ -267,7 +265,6 @@ begin
           X2_cwm_i <= '0';
         end if;
 
-
         if W3_baz = '1' then                                       -- counter Baz
           W3_var <= unsigned(W3_turn);
           if W3_turn = "00000000000000000000000000000000" then
@@ -335,7 +332,6 @@ begin
 
         end if;  -- debct_blrb
 
-
         -- comment
         if debct_zz1pb = '0' then
           debct_cwm_i <= '0';
diff --git a/examples/expr.vhd b/examples/expr.vhd
index 24b3885..81e8ab1 100644
--- a/examples/expr.vhd
+++ b/examples/expr.vhd
@@ -1,6 +1,5 @@
 library IEEE;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
 use ieee.numeric_std.all;
 
 entity expr is port( reset, sysclk, ival : in std_logic);
@@ -16,13 +15,13 @@ begin
   -- drive input status
   input_status <=    -- top bits
                            (foo(9 downto 4) &
-                            (( baz(3 downto 0) and foo(3 downto 0) or
-                             (not baz(3 downto 0) and bam(3 downto 0)))));
+                            (( (baz(2 downto 0) and foo(3 downto 0)) or
+                             (not baz(2 downto 0) and bam(3 downto 0)))));
   -- drive based on foo
-  out_i <=
+  out_i(4) <=
     -- if secondary enabl is set then drive aux out
     (enable and (aux xor outy)) or
-    -- if debug is enabled               
+    -- if debug is enabled
     (debug and dv and not enable) or
     -- otherwise we drive reg
     (not debug and not enable and value);
@@ -33,7 +32,7 @@ begin
     if( reset /= '0' ) then
       foo <= (others => '0');
     elsif( sysclk'event and sysclk = '0' ) then
-      foo(3*(2-1)) <= (4*(1+2));
+      foo(3*(2-1)) <= baz(1*(1+2)-2);
       bam(foo'range) <= foo;
     end if;
   end process;
diff --git a/examples/for.vhd b/examples/for.vhd
index 796f209..c18c2e3 100644
--- a/examples/for.vhd
+++ b/examples/for.vhd
@@ -1,6 +1,5 @@
 library IEEE;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
 use ieee.numeric_std.all;
 entity forp is port(
   reset, sysclk : in std_logic
diff --git a/examples/generate.vhd b/examples/generate.vhd
index 56d5d3c..4abdbf6 100644
--- a/examples/generate.vhd
+++ b/examples/generate.vhd
@@ -1,5 +1,5 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all;
 entity gen is   generic(
   bus_width : integer := 15;
   TOP_GP2 : integer:= 0
diff --git a/examples/generic.vhd b/examples/generic.vhd
index 6ffc208..e3b6801 100644
--- a/examples/generic.vhd
+++ b/examples/generic.vhd
@@ -1,5 +1,6 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
+
 entity test is
   generic(
     dog_width : std_logic_vector(7 downto 0) := "10101100";
@@ -22,11 +23,11 @@ begin
                         "11100010" when "101",
                         (others => '1') when "010",
                         (others => '0') when "011",
-                        a + b + '1' when others;
+                        std_logic_vector(unsigned(a) + unsigned(b)) when others;
   code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
   
   foo <= (others => '0');
   egg <= (others => '0');
   baz <= (others => '1');
-  complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001";
+  complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001";
 end rtl;
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 0ddd610..1132554 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -1,5 +1,5 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all;
 entity test is
 generic(
   rst_val   : std_logic := '0';
diff --git a/examples/gh_fifo_async16_sr.vhd b/examples/gh_fifo_async16_sr.vhd
index 1098bc3..0c5183f 100644
--- a/examples/gh_fifo_async16_sr.vhd
+++ b/examples/gh_fifo_async16_sr.vhd
@@ -18,8 +18,7 @@
 

 library IEEE;

 use IEEE.std_logic_1164.all;

-use IEEE.std_logic_unsigned.all;

-USE ieee.std_logic_arith.all;

+USE ieee.numeric_std.all;

 

 entity gh_fifo_async16_sr is

 	GENERIC (data_width: INTEGER :=8 ); -- size of data bus

@@ -69,12 +68,12 @@ process (clk_WR)
 begin			  

 	if (rising_edge(clk_WR)) then

 		if ((WR = '1') and (ifull = '0')) then

-			ram_mem(CONV_INTEGER(add_WR(3 downto 0))) <= D;

+			--ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D;

 		end if;

 	end if;		

 end process;

 

-	Q <= ram_mem(CONV_INTEGER(add_RD(3 downto 0)));

+	--Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0))));

 

 -----------------------------------------

 ----- Write address counter -------------

@@ -84,7 +83,7 @@ end process;
 	             '0' when (WR = '0') else

 	             '1';

 

-	n_add_WR <= add_WR + x"1";

+	n_add_WR <= std_logic_vector(unsigned(add_WR) + x"1");

 				 

 process (clk_WR,rst)

 begin 

@@ -126,7 +125,7 @@ end process;
 	             '0' when (RD = '0') else

 	             '1';

 				 

-	n_add_RD <= add_RD + x"1";

+	n_add_RD <= std_logic_vector(unsigned(add_RD) + x"1");

 				 

 process (clk_RD,rst)

 begin 

diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd
index 651947a..dbc0a98 100644
--- a/examples/ifchain.vhd
+++ b/examples/ifchain.vhd
@@ -1,9 +1,11 @@
 LIBRARY IEEE;
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all;
+
 entity test is port(
   clk, rstn : in std_logic
 );
 end test;
+
 architecture rtl of test is
   type   t is array (3 downto 0) of std_logic_vector(31 downto 0);
   signal a : std_logic_vector(3 downto 0);
@@ -11,12 +13,13 @@ architecture rtl of test is
   signal status : std_logic;
   signal c : t;
 begin
+
   process(clk) begin
     if clk'event and clk = '1' then
       if  b(1) & a(3 downto 2)  = "001" then
-        status <= "1";
-        c(0) <= x"FFFF";
-      end if;          
+        status <= '1';
+        c(0) <= x"FFFFFFFF";
+      end if;
     end if;
   end process;
 
diff --git a/examples/test.vhd b/examples/test.vhd
index 0532a7b..bcc2968 100644
--- a/examples/test.vhd
+++ b/examples/test.vhd
@@ -7,7 +7,7 @@
 
 LIBRARY IEEE;
 
-USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
+USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
 
 entity test is port(
   -- Inputs
@@ -135,7 +135,7 @@ begin
                         "11100010" when "101",
                         (others => '1') when "010",
                         (others => '0') when "011",
-                        a + b + '1' when others;
+                        std_logic_vector(unsigned(a) + unsigned(b)) when others;
   code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
   
   -- Asynch process
@@ -183,9 +183,9 @@ begin
     dout => memdin
   );
 
-  complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001";
+  complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001";
 
-  enf <= '1' when a = "1101111" + load and c < "1000111" else '0';
+  enf <= '1' when c < "1000111" else '0';
   eno <= enf;
 
 end rtl;
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index dd755b7..e4e724e 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -42,15 +42,15 @@ wire [8:0] input_status;
 wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
 
   // drive input status
-  assign input_status = {foo[9:4],((baz[3:0] & foo[3:0] | (( ~baz[3:0] & bam[3:0]))))};
+  assign input_status = {foo[9:4],((((baz[2:0] & foo[3:0])) | (( ~baz[2:0] & bam[3:0]))))};
   // drive based on foo
-  assign out_i = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
+  assign out_i[4] = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
   // not drive
   always @(negedge reset or negedge sysclk) begin
     if((reset != 1'b0)) begin
       foo <= {14{1'b0}};
     end else begin
-      foo[3 * ((2 - 1))] <= (4 * ((1 + 2)));
+      foo[3 * ((2 - 1))] <= baz[1 * ((1 + 2)) - 2];
       bam[13:0] <= foo;
     end
   end
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index fe2e5c4..df0e7bb 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -60,7 +60,7 @@ wire [31:0] complex;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b1;
+      default : code[9:2] <= (((a)) + ((b)));
     endcase
   end
 
@@ -68,6 +68,6 @@ wire [31:0] complex;
   assign foo = {(((1 + 1))-((0))+1){1'b0}};
   assign egg = {78{1'b0}};
   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
-  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
+  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
 
 endmodule
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index 7128d4e..b01f808 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -83,7 +83,7 @@ wire full;
 
 
 
-reg [data_width - 1:0] ram_mem[15:0];
+wire [data_width - 1:0] ram_mem[15:0];
 wire iempty;
 wire ifull;
 wire add_WR_CE;
@@ -107,16 +107,16 @@ reg isrst_r;
   //------------------------------------------
   always @(posedge clk_WR) begin
     if(((WR == 1'b1) && (ifull == 1'b0))) begin
-      ram_mem[(add_WR[3:0])] <= D;
+      //ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D;
     end
   end
 
-  assign Q = ram_mem[(add_RD[3:0])];
+  //Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0))));
   //---------------------------------------
   //--- Write address counter -------------
   //---------------------------------------
   assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_WR = add_WR + 4'h1;
+  assign n_add_WR = (((add_WR)) + 4'h1);
   always @(posedge clk_WR or posedge rst) begin
     if((rst == 1'b1)) begin
       add_WR <= {5{1'b0}};
@@ -149,7 +149,7 @@ reg isrst_r;
   //--- Read address counter --------------
   //---------------------------------------
   assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_RD = add_RD + 4'h1;
+  assign n_add_RD = (((add_RD)) + 4'h1);
   always @(posedge clk_RD or posedge rst) begin
     if((rst == 1'b1)) begin
       add_RD <= {5{1'b0}};
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index feddd03..b719b82 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -41,7 +41,7 @@ reg [31:0] c[3:0];
   always @(posedge clk) begin
     if({b[1],a[3:2]} == 3'b001) begin
       status <= 1'b1;
-      c[0] <= 16'hFFFF;
+      c[0] <= 32'hFFFFFFFF;
     end
   end
 
diff --git a/translated_examples/test.v b/translated_examples/test.v
index e7ce5a2..c8f4d53 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -187,7 +187,7 @@ reg [1:0] colour;
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b1;
+      default : code[9:2] <= (((a)) + ((b)));
     endcase
   end
 
@@ -238,8 +238,8 @@ reg [1:0] colour;
     // Outputs
     .dout(memdin));
 
-  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
-  assign enf = a == (7'b1101111 + load) && c < 7'b1000111 ? 1'b1 : 1'b0;
+  assign complex = {enf,((3'b110 * ((load)))),qtd[3:0],base,5'b11001};
+  assign enf = c < 7'b1000111 ? 1'b1 : 1'b0;
   assign eno = enf;
 
 endmodule