vhd2vl-2.4

19 files changed, 509 insertions, 190 deletions

diff --git a/README.txt b/README.txt
index 430d64d..f5806aa 100644
--- a/README.txt
+++ b/README.txt
@@ -1,4 +1,4 @@
-VHD2VL v2.2 README.txt
+VHD2VL v2.4 README.txt
 
 Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
 It does not support the full VHDL grammar - most of the testbench
@@ -12,6 +12,7 @@ tool to compare it to the original VHDL!
 The home page for (at least for this version of) vhd2vl is
   http://doolittle.icarus.com/~larry/vhd2vl/
 
+
 1.0 HOW TO BUILD AND INSTALL vhd2vl:
 
 To build, just type 'make' in the src directory.
@@ -32,6 +33,11 @@ or
 The two are equivalent when everything works.  The latter has some
 advantages when handling errors within a Makefile.
 
+There are a few of options available on the command line:
+  -d  turn on debugging within the yacc (bison) parser
+  -g1995  (default) use traditional Verilog module declaration style
+  -g2001  use Verilog-2001 module declaration style
+
 
 3.0 TROUBLESHOOTING:
 
@@ -57,6 +63,12 @@ vhd2vl.output. If you need to change the grammar, then running vhd2vl
 with the '-d' option will cause vhd2vl to trace how it is parsing the
 input file.  See the bison documentation for more details.
 
+To test a copy of vhdl for regressions against the example code shipped,
+  mkdir test
+  (cd examples && for f in *.vhd; do vhd2vl $f ../test/${f%%.vhd}.v; done)
+  diff -u translated_examples test | less
+from this directory using a Bourne-style shell.
+
 
 4.0 MISSING FEATURES AND KNOWN INCORRECT OUTPUT:
 
@@ -84,3 +96,9 @@ VHDL is case insensitive, vhd2vl is case retentive, and Verilog is case
   sensitive.  If you're sloppy with case in the original VHDL, the
   resulting Verilog will have compile-time warnings or errors.  See
   the comments about vhd2vl-2.1 in the changes file.
+
+Doesn't necessarily get clock edge sensitivities right if there is more
+  than one clock in the list
+
+Totally broken handling of text in generic mappings, as Xilinx is wont to
+  use for their primitives and wrappers
diff --git a/changes b/changes
index d9872f6..bfe69d6 100644
--- a/changes
+++ b/changes
@@ -1,3 +1,23 @@
+Changes 2.3 to 2.4 (Larry Doolittle, November 2010)
+
+Grammar:
+  * drop DOS-style returns at end of comments
+  * allow FLOAT in expressions (maybe a mistake)
+  * fixed regression in "others" handling since 2.1
+  * don't crash with "others" in instantiation (Verilog result is still broken)
+  (the following were submitted by Shankar Giri)
+  * Verilog 2001 module declaration (runtime selectable, use -g2001)
+  * named generate block support for XST compatibility
+  * support for array of vectors
+  * some generic enhancements on architecture body
+
+Coding:
+  * CLI enhancement (added more switches)
+  * factor out push_clkedge(), pull_clkedge()
+  * fully const-correct
+  * minor whitespace and coding style cleanup
+
+
 Changes 2.2 to 2.3 (Larry Doolittle, May 2010)
 
 Grammar:
@@ -12,9 +32,10 @@ Grammar:
   * accept integer ranges, but ignore the range and give a warning
 
 Coding:
-  * list def.h properly in makefile 
+  * list def.h properly in makefile
   * factor out new_vrange(), addnest(), setup_port()
 
+
 Changes 1.2 to 2.2 (Larry Doolittle, February 2009)
 
 Merge extensive changes from Mark Gonzales' version 2.0.  Thanks, Mark!
@@ -83,12 +104,12 @@ Grammar:
   * allow IS syntactic sugar in COMPONENT declaration
   * add a bunch of "rem"s to the grammar
   * handle inout better
-  * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector" 
+  * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector"
 
 Operation:
   * more complete handling of argc/argv
   * if error happened, return 1 from main and remove incorrect/incomplete output files
-  * avoid insinuating that output Verilog is covered by GPL 
+  * avoid insinuating that output Verilog is covered by GPL
 
 Coding:
   * increase gcc warning level
diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd
index 161ba34..651947a 100644
--- a/examples/ifchain.vhd
+++ b/examples/ifchain.vhd
@@ -5,14 +5,17 @@ entity test is port(
 );
 end test;
 architecture rtl of test is
+  type   t is array (3 downto 0) of std_logic_vector(31 downto 0);
   signal a : std_logic_vector(3 downto 0);
   signal b : std_logic_vector(3 downto 0);
   signal status : std_logic;
+  signal c : t;
 begin
   process(clk) begin
     if clk'event and clk = '1' then
       if  b(1) & a(3 downto 2)  = "001" then
         status <= "1";
+        c(0) <= x"FFFF";
       end if;          
     end if;
   end process;
diff --git a/src/def.h b/src/def.h
index afc93dc..f12de94 100644
--- a/src/def.h
+++ b/src/def.h
@@ -71,9 +71,14 @@ typedef struct expdata {
 typedef struct sglist {
   char *name; /* Signal name */
   char *type; /* Reg or wire */
+  const char *dir; /* input, output, inout */
   vrange *range; /* Signal size */
   struct sglist *next;
 } sglist;
 
+typedef struct blknamelist {
+  char *name; /* Optional name */
+  struct blknamelist *next;
+} blknamelist;
 
 #endif
diff --git a/src/makefile b/src/makefile
index 652d15b..ac564a4 100644
--- a/src/makefile
+++ b/src/makefile
@@ -1,5 +1,20 @@
+# Leave off -Wundef -Wredundant-decls -Wtraditional-conversion until flex
+# and bison get cleaned up.  Our code is nearly fine now.
+# Use -W for now instead of the more modern -Wextra, since lots of people
+# still use older compilers.
+# Use the following for development
+# WARNS = -Wall -W -Wshadow -Wpointer-arith -Wcast-qual -Wpointer-arith -Wcast-align -Wcast-qual -Wsign-compare -Wwrite-strings -Wstrict-overflow=5 -Wformat=2 -pedantic
+
+# simplified version for general use, so as not to look so intimidating
+WARNS = -Wall -W
+
+# any of the following three should work:
+STANDARD =
+#STANDARD = --std=c89 -D_POSIX_C_SOURCE -D_BSD_SOURCE
+#STANDARD = --std=c99 -D_POSIX_C_SOURCE -D_BSD_SOURCE
+
 vhd2vl : lex.yy.c vhd2vl.tab.c
-	gcc -Wall -Wshadow -W -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl
+	gcc ${STANDARD} ${WARNS} -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl
 
 vhd2vl.tab.c : vhd2vl.y def.h
 	bison -d -v -t vhd2vl.y
diff --git a/src/vhd2vl.l b/src/vhd2vl.l
index 4fef561..d3604c3 100644
--- a/src/vhd2vl.l
+++ b/src/vhd2vl.l
@@ -33,8 +33,8 @@ extern int lineno;
 
 extern int skipRem;
 
-void getstring(int skip);
-void getbasedstring(int skip);
+void getstring(unsigned skip);
+void getbasedstring(unsigned skip);
 
 %}
 %%
@@ -42,18 +42,21 @@ void getbasedstring(int skip);
 [ \t] {;}
 
 "--".*\n {
+  lineno++;
   if (skipRem == 0) {
-    /* sometimes comments should be dropped by lex - 
+    /* sometimes comments should be dropped by lex -
      * e.g. in expressions - this makes the grammar much simpler
      */
-    yylval.txt=malloc(strlen(yytext)+1);
+    size_t l=strlen(yytext);
+    yylval.txt=malloc(l+1);
     strcpy(yylval.txt, yytext);
-    yylval.txt[0]='/'; 
+    yylval.txt[0]='/';
     yylval.txt[1]='/';
-    lineno++; 
+    if(yylval.txt[l-2]=='\r') {
+       yylval.txt[l-2]='\n';
+       yylval.txt[l-1]='\0';
+    }
     return REM;
-  } else {
-    lineno++; 
   }
 }
 "library ".*\n {lineno++;}
@@ -143,24 +146,27 @@ void getbasedstring(int skip);
   return NATURAL;
 }
 
+[0-9]+\.[0-9]+ {
+  getstring(0);
+  return FLOAT;
+}
+
 . { return yytext[0]; }
 
 %%
 
-void getstring(int skip){
+void getstring(unsigned skip){
 /* Gets a string excluding " or ' */
-int i;
-
+  unsigned i;
   for(i=skip; yytext[i]!='"' && yytext[i]!='\'' && yytext[i]!=0; i++);
   yytext[i]=0;
   yylval.txt=malloc(i+1);
   strcpy(yylval.txt, yytext+skip);
 }
 
-void getbasedstring(int skip){
+void getbasedstring(unsigned skip){
 /* Gets a string excluding # */
-int i;
-
+  unsigned i;
   for(i=skip; yytext[i]!='#' && yytext[i]!=0; i++);
   yytext[i]=0;
   yylval.txt=malloc(i+1);
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index e3b823b..b4d6274 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -1,8 +1,9 @@
 /*
-    vhd2vl v2.3
+    vhd2vl v2.4
     VHDL to Verilog RTL translator
     Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com
     Modifications (C) 2006 Mark Gonzales - PMC Sierra Inc
+    Modifications (C) 2010 Shankar Giri
     Modifications (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 
     This program is free software; you can redistribute it and/or modify
@@ -29,7 +30,9 @@
 #include "def.h"
 
 int yylex(void);
-void yyerror(char *s);
+void yyerror(const char *s);
+
+int vlog_ver=0;  /* default is -g1995 */
 
 /* You will of course want to tinker with this if you use a debugging
  * malloc(), otherwise all the line numbers will point here.
@@ -49,10 +52,11 @@ int lineno=1;
 sglist *io_list=NULL;
 sglist *sig_list=NULL;
 sglist *type_list=NULL;
+blknamelist *blkname_list=NULL;
 
 /* need a stack of clock-edges because all edges are processed before all processes are processed.
  * Edges are processed in source file order, processes are processed in reverse source file order.
- * The original scheme of just one clkedge variable makes all clocked processes have the edge sensitivity 
+ * The original scheme of just one clkedge variable makes all clocked processes have the edge sensitivity
  * of the last clocked process in the file.
  */
 int clkedges[MAXEDGES];
@@ -134,7 +138,7 @@ slist *copysl(slist *sl){
   return NULL;
 }
 
-slist *addtxt(slist *sl, char *s){
+slist *addtxt(slist *sl, const char *s){
   slist *p;
 
   if(s == NULL)
@@ -205,7 +209,7 @@ slist *addvec(slist *sl, char *s){
 }
 
 slist *addvec_base(slist *sl, char *b, char *s){
-  char *base_str="'b ";
+  const char *base_str="'b ";
   int base_mult=1;
   if (strcasecmp(b,"X") == 0) {
      base_str="'h "; base_mult=4;
@@ -255,6 +259,29 @@ slist *addpar_snug(slist *sl, vrange *v){
   return sl;
 }
 
+/* This function handles array of vectors in signal lists */
+slist *addpar_snug2(slist *sl, vrange *v, vrange *v1){
+  if(v->nlo != NULL) {   /* indexes are simple expressions */
+    sl=addtxt(sl,"[");
+    if(v->nhi != NULL){
+      sl=addsl(sl,v->nhi);
+      sl=addtxt(sl,":");
+    }
+    sl=addsl(sl,v->nlo);
+    sl=addtxt(sl,"]");
+  }
+  if(v1->nlo != NULL) {   /* indexes are simple expressions */
+    sl=addtxt(sl,"[");
+    if(v1->nhi != NULL){
+      sl=addsl(sl,v1->nhi);
+      sl=addtxt(sl,":");
+    }
+    sl=addsl(sl,v1->nlo);
+    sl=addtxt(sl,"]");
+  }
+  return sl;
+}
+
 slist *addpost(slist *sl, vrange *v){
   if(v->xlo != NULL) {
     sl=addtxt(sl,"[");
@@ -268,7 +295,7 @@ slist *addpost(slist *sl, vrange *v){
   return sl;
 }
 
-slist *addwrap(char *l,slist *sl,char *r){
+slist *addwrap(const char *l,slist *sl,const char *r){
 slist *s;
   s=addtxt(NULL,l);
   s=addsl(s,sl);
@@ -282,7 +309,7 @@ expdata *addnest(struct expdata *inner)
   if (inner->op == 'c') {
     e->sl=addwrap("{",inner->sl,"}");
   } else {
-    e->sl=addwrap("(",inner->sl,")"); 
+    e->sl=addwrap("(",inner->sl,")");
   }
   return e;
 }
@@ -312,9 +339,9 @@ char *sbottom(slist *sl){
   return sl->data.txt;
 }
 
-char *inout_string(int type)
+const char *inout_string(int type)
 {
-  char *name=NULL;
+  const char *name=NULL;
   switch(type) {
     case 0: name="input"  ; break;
     case 1: name="output" ; break;
@@ -324,7 +351,7 @@ char *inout_string(int type)
   return name;
 }
 
-int prec(char op){
+int prec(int op){
   switch(op){
   case 'o': /* others */
     return 9;
@@ -359,7 +386,7 @@ int prec(char op){
   }
 }
 
-expdata *addexpr(expdata *expr1,char op,char* opstr,expdata *expr2){
+expdata *addexpr(expdata *expr1,int op,const char* opstr,expdata *expr2){
 slist *sl1,*sl2;
   if(expr1 == NULL)
     sl1=NULL;
@@ -389,7 +416,7 @@ slist *sl1,*sl2;
   return expr1;
 }
 
-void slTxtReplace(slist *sl, char *match, char *replace){
+void slTxtReplace(slist *sl, const char *match, const char *replace){
   if(sl){
     slTxtReplace(sl->slst, match, replace);
     switch(sl->type) {
@@ -398,18 +425,40 @@ void slTxtReplace(slist *sl, char *match, char *replace){
       break;
     case 1 :
       if (strcmp(sl->data.txt, match) == 0) {
-        sl->data.txt = replace;
+        sl->data.txt = strdup(replace);
       }
       break;
     case 3 :
       if (strcmp(*(sl->data.ptxt), match) == 0) {
-        *(sl->data.ptxt) = replace;
+        *(sl->data.ptxt) = strdup(replace);
       }
       break;
     }
   }
 }
 
+
+/* XXX todo: runtime engage clkedge debug */
+void push_clkedge(int val, const char *comment)
+{
+  if (0) fprintf(stderr,"clock event push: line=%d clkptr=%d, value=%d (%s)\n",lineno,clkptr,val,comment);
+  clkedges[clkptr++]=val;
+  assert(clkptr < MAXEDGES);
+}
+
+int pull_clkedge(slist *sensitivities)
+{
+  int clkedge;
+  assert(clkptr>0);
+  clkedge = clkedges[--clkptr];
+  if (0) {
+     fprintf(stderr,"clock event pull: value=%d, sensistivity list = ", clkedge);
+     fslprint(stderr,sensitivities);
+     fprintf(stderr,"\n");
+  }
+  return clkedge;
+}
+
 /* XXX maybe it's a bug that some uses don't munge clocks? */
 slist *add_always(slist *sl, slist *sensitivities, slist *decls, int munge)
 {
@@ -417,7 +466,7 @@ slist *add_always(slist *sl, slist *sensitivities, slist *decls, int munge)
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"always @(");
            if (munge) {
-             clkedge = clkedges[--clkptr];
+             clkedge = pull_clkedge(sensitivities);
              if(clkedge) {
                sl=addtxt(sl,"posedge ");
                /* traverse $4->sl replacing " or " with " or posedge " if there is a clockedge */
@@ -452,6 +501,11 @@ void fixothers(slist *size_expr, slist *sl) {
       slist *p;
       slist *size_copy = xmalloc(sizeof(slist));
       size_copy = copysl(size_expr);
+      if (0) {
+        fprintf(stderr,"fixothers type 4 size_expr ");
+        fslprint(stderr,size_expr);
+        fprintf(stderr,"\n");
+      }
       p = addtxt(NULL, "1'b");
       p = addtxt(p, sl->data.txt);
       p = addwrap("{",p,"}");
@@ -470,6 +524,11 @@ void findothers(slval *sgin,slist *sl){
   sglist *sg = NULL;
   int size = -1;
   int useExpr=0;
+  if (0) {
+    fprintf(stderr,"findothers lhs ");
+    fslprint(stderr,sgin->sl);
+    fprintf(stderr,", sgin->val %d\n", sgin->val);
+  }
   if(sgin->val>0) {
     size=sgin->val;
   } else if (sgin->range != NULL) {
@@ -503,9 +562,9 @@ void findothers(slval *sgin,slist *sl){
     }  /* if(sg) */
   }
   if (!useExpr) {
+    slist *p;
     assert(size>0);
     /* use size */
-    slist *p;
     p = addval(NULL,size);
     fixothers(p,sl);
   }
@@ -573,23 +632,54 @@ slist *output_timescale(slist *sl)
 slist *setup_port(sglist *s_list, int dir, vrange *type) {
   slist *sl;
   sglist *p;
-  sl=addtxt(NULL,inout_string(dir));
-  sl=addpar(sl,type);
+  if (vlog_ver == 1) {
+    sl=addtxt(NULL,NULL);
+  }
+  else {
+    sl=addtxt(NULL,inout_string(dir));
+    sl=addpar(sl,type);
+  }
   p=s_list;
   for(;;){
     p->type=wire;
+    if (vlog_ver == 1) p->dir=inout_string(dir);
     p->range=type;
-    sl=addtxt(sl,p->name);
+    if (vlog_ver == 0) sl=addtxt(sl, p->name);
     if(p->next==NULL)
       break;
     p=p->next;
-    sl=addtxt(sl,", ");
+    if (vlog_ver == 0) sl=addtxt(sl,", ");
   }
-  sl=addtxt(sl,";\n");
+  if (vlog_ver == 0) sl=addtxt(sl,";\n");
   p->next=io_list;
   io_list=s_list;
   return sl;
 }
+
+slist *emit_io_list(slist *sl)
+{
+              sglist *p;
+              sl=addtxt(sl,"(\n");
+              p=io_list;
+              for(;;){
+                if (vlog_ver == 1) {
+                  sl=addtxt(sl,p->dir);
+                  sl=addtxt(sl," ");
+                  sl=addptxt(sl,&(p->type));
+                  sl=addpar(sl,p->range);
+                }
+                sl=addtxt(sl,p->name);
+                p=p->next;
+                if(p)
+                  sl=addtxt(sl,",\n");
+                else{
+                  sl=addtxt(sl,"\n");
+                  break;
+                }
+              }
+              sl=addtxt(sl,");\n\n");
+              return sl;
+}
 %}
 
 %union {
@@ -612,7 +702,7 @@ slist *setup_port(sglist *s_list, int dir, vrange *type) {
 %token <txt> AFTER AND OR XOR MOD
 %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
 %token <txt> STRING NAME RANGE NULLV OPEN
-%token <txt> CONVFUNC_1 CONVFUNC_2 BASED
+%token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT
 %token <n> NATURAL
 
 %type <n> trad
@@ -621,7 +711,7 @@ slist *setup_port(sglist *s_list, int dir, vrange *type) {
 %type <sl> a_decl a_body p_decl oname
 %type <sl> map_list map_item mvalue sigvalue
 %type <sl> generic_map_list generic_map_item
-%type <sl> conf exprc sign_list p_body optname
+%type <sl> conf exprc sign_list p_body optname gen_optname
 %type <sl> edge
 %type <sl> elsepart wlist wvalue cases
 %type <sl> with_item with_list
@@ -632,7 +722,8 @@ slist *setup_port(sglist *s_list, int dir, vrange *type) {
 %type <e> expr
 %type <e> simple_expr
 %type <ss> signal
-%type <txt> opt_is opt_generic opt_entity opt_architecture
+%type <txt> opt_is opt_generic opt_entity opt_architecture opt_begin
+%type <txt> generate endgenerate
 
 %right '='
 /* Logic operators: */
@@ -649,14 +740,14 @@ slist *setup_port(sglist *s_list, int dir, vrange *type) {
 %left  '+'  '-'  '&'
 %left  '*'  '/'
 %right UMINUS  UPLUS  NOTL  NOT
-
 %error-verbose
 
 /* rule for "...ELSE IF edge THEN..." causes 1 shift/reduce conflict */
-%expect 1
+/* rule for opt_begin causes 1 shift/reduce conflict */
+%expect 2
 
-/* glr-parser is needed because processes can start with if statements, but 
- * not have edges in them - more than one level of look-ahead is needed in that case 
+/* glr-parser is needed because processes can start with if statements, but
+ * not have edges in them - more than one level of look-ahead is needed in that case
  * %glr-parser
  * unfortunately using glr-parser causes slists to become self-referential, causing core dumps!
  */
@@ -714,36 +805,31 @@ opt_entity   : /* Empty */ {$$=NULL;} | ENTITY ;
 
 opt_architecture   : /* Empty */ {$$=NULL;} | ARCHITECTURE ;
 
+opt_begin    : /* Empty */ {$$=NULL;} | BEGN;
+
+generate       : GENERATE opt_begin;
+
+endgenerate    : END GENERATE;
+
 /* tell the lexer to discard or keep comments ('-- ') - this makes the grammar much easier */
 norem : /*Empty*/ {skipRem = 1;}
 yesrem : /*Empty*/ {skipRem = 0;}
 
 /* Entity */
 /*          1      2    3  4     5  6   7         8   9  10  11  12    13 */
-entity    : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END opt_entity oname ';' {
+entity    : ENTITY NAME IS rem PORT '(' rem portlist ')' ';' rem END opt_entity oname ';' {
             slist *sl;
             sglist *p;
               sl=addtxt(NULL,"\nmodule ");
               sl=addtxt(sl,$2); /* NAME */
-              sl=addtxt(sl,"(\n");
               /* Add the signal list */
-              p=io_list;
-              for(;;){
-                sl=addtxt(sl,p->name);
-                p=p->next;
-                if(p)
-                  sl=addtxt(sl,",\n");
-                else{
-                  sl=addtxt(sl,"\n");
-                  break;
-                }
-              }
-              sl=addtxt(sl,");\n\n");
-              sl=addsl(sl,$6); /* rem */
-              sl=addsl(sl,$7); /* portlist */
+              sl=emit_io_list(sl);
+              sl=addsl(sl,$7); /* rem */
+              sl=addsl(sl,$8); /* portlist */
               sl=addtxt(sl,"\n");
               p=io_list;
-              do{
+              if (vlog_ver == 0) {
+                do{
                 sl=addptxt(sl,&(p->type));
                 /*sl=addtxt(sl,p->type);*/
                 sl=addpar(sl,p->range);
@@ -751,9 +837,10 @@ entity    : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END opt_entity onam
                 /* sl=addpost(sl,p->range); */
                 sl=addtxt(sl,";\n");
                 p=p->next;
-              } while(p!=NULL);
+                } while(p!=NULL);
+              }
               sl=addtxt(sl,"\n");
-              sl=addsl(sl,$10); /* rem2 */
+              sl=addsl(sl,$11); /* rem2 */
               $$=addtxt(sl,"\n");
             }
  /*         1      2    3  4       5        6   7  8         9  10  11   12      13  14  15       16   17 18  19  20  21    22 */
@@ -763,20 +850,7 @@ entity    : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END opt_entity onam
               if (0) fprintf(stderr,"matched ENTITY GENERIC\n");
               sl=addtxt(NULL,"\nmodule ");
               sl=addtxt(sl,$2); /* NAME */
-              sl=addtxt(sl,"(\n");
-              /* Add the signal list */
-              p=io_list;
-              for(;;){
-                sl=addtxt(sl,p->name);
-                p=p->next;
-                if(p)
-                  sl=addtxt(sl,",\n");
-                else{
-                  sl=addtxt(sl,"\n");
-                  break;
-                }
-              }
-              sl=addtxt(sl,");\n\n");
+              sl=emit_io_list(sl);
               sl=addsl(sl,$7);  /* rem */
               sl=addsl(sl,$8);  /* genlist */
               sl=addsl(sl,$11); /* rem */
@@ -784,14 +858,16 @@ entity    : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END opt_entity onam
               sl=addsl(sl,$16); /* portlist */
               sl=addtxt(sl,"\n");
               p=io_list;
-              do{
+              if (vlog_ver == 0) {
+                do{
                 sl=addptxt(sl,&(p->type));
                 /*sl=addtxt(sl,p->type);*/
                 sl=addpar(sl,p->range);
                 sl=addtxt(sl,p->name);
                 sl=addtxt(sl,";\n");
                 p=p->next;
-              } while(p!=NULL);
+                } while(p!=NULL);
+              }
               sl=addtxt(sl,"\n");
               sl=addsl(sl,$19); /* rem2 */
               $$=addtxt(sl,"\n");
@@ -986,8 +1062,8 @@ vec_range : simple_expr updown simple_expr {
                 }
               } else {
                 /* make an expression to calculate the width of this vrange:
-                 * create an expression that calculates: 
-                 *   size expr = (simple_expr1) - (simple_expr2) + 1 
+                 * create an expression that calculates:
+                 *   size expr = (simple_expr1) - (simple_expr2) + 1
                  */
                 expdata *size_expr1  = xmalloc(sizeof(expdata));
                 expdata *size_expr2  = xmalloc(sizeof(expdata));
@@ -1079,6 +1155,36 @@ a_decl    : {$$=NULL;}
               sig_list=$3;
               $$=addrem(sl,$7);
             }
+          | a_decl SIGNAL s_list ':' type ':' '=' expr ';' rem {
+            sglist *sg;
+            slist *sl;
+            int size;
+
+              if($5->vtype==tSUBSCRIPT)
+                size=1;
+              else
+                size=-1;
+              sl=$1;
+              sg=$3;
+              for(;;){
+                sg->type=wire;
+                sg->range=$5;
+                sl=addptxt(sl,&(sg->type));
+                sl=addpar(sl,$5);
+                sl=addtxt(sl,sg->name);
+                sl=addpost(sl,$5);
+                sl=addtxt(sl," = ");
+                sl=addsl(sl,$8->sl);
+                sl=addtxt(sl,";");
+                if(sg->next == NULL)
+                  break;
+                sl=addtxt(sl," ");
+                sg=sg->next;
+              }
+              sg->next=sig_list;
+              sig_list=$3;
+              $$=addrem(sl,$10);
+            }
           | a_decl CONSTANT NAME ':' type ':' '=' expr ';' rem {
             slist * sl;
               sl=addtxt($1,"parameter ");
@@ -1204,6 +1310,18 @@ a_body : rem {$$=addind($1);}
            sl=addtxt(sl,";\n");
            $$=addsl(sl,$9);
          }
+       | rem BEGN signal '<' '=' rem norem sigvalue yesrem a_body END NAME ';' {
+         slist *sl;
+           sl=addsl($1,indents[indent]);
+           sl=addtxt(sl,"assign ");
+           sl=addsl(sl,$3->sl);
+           findothers($3,$8);
+           free($3);
+           sl=addtxt(sl," = ");
+           sl=addsl(sl,$8);
+           sl=addtxt(sl,";\n");
+           $$=addsl(sl,$10);
+         }
        /* 1   2     3    4    5   6       7       8   9     10     11 */
        | rem WITH expr SELECT rem yeswith signal '<' '=' with_list a_body {
          slist *sl;
@@ -1346,24 +1464,34 @@ a_body : rem {$$=addind($1);}
 
        /* note vhdl does not allow an else in an if generate statement */
        /* 1       2   3          4       5       6        7     8        9   10   11  12 */
-       | optname IF exprc GENERATE  doindent a_body  unindent END GENERATE oname ';' a_body {
+       | gen_optname IF exprc generate  doindent a_body  unindent endgenerate oname ';' a_body {
          slist *sl;
+         blknamelist *tname_list;
            sl=addsl($1,indents[indent]);
            sl=addtxt(sl,"generate ");
            sl=addtxt(sl,"if (");
            sl=addsl(sl,$3); /* exprc */
-           sl=addtxt(sl,") begin\n");
+           sl=addtxt(sl,") begin: ");
+           tname_list=blkname_list;
+           sl=addtxt(sl,tname_list->name);
+           blkname_list=blkname_list->next;
+           if (tname_list!=NULL) {
+           free(tname_list->name);
+           free(tname_list);
+           }
+           sl=addtxt(sl,"\n");
            sl=addsl(sl,indents[indent]);
            sl=addsl(sl,$6);   /* a_body:1 */
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"end\n");
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"endgenerate\n");
-           $$=addsl(sl,$12);    /* a_body:2 */
+           $$=addsl(sl,$11);    /* a_body:2 */
          }
-       /* 1       2       3    4 5    6   7     8        9      10      11       12    13     14    15  16 */
-       | optname FOR  signal IN expr TO expr GENERATE  doindent a_body  unindent END GENERATE oname ';' a_body {
+       /* 1       2       3    4 5    6   7  8        9      10      11       12    13     14    15  16 */
+       | gen_optname FOR  signal IN expr TO expr generate doindent a_body  unindent endgenerate oname ';' a_body {
          slist *sl;
+         blknamelist *tname_list;
            sl=addsl($1,indents[indent]);
            sl=addtxt(sl,"genvar ");
            sl=addsl(sl,$3->sl); /* signal */
@@ -1382,19 +1510,32 @@ a_body : rem {$$=addind($1);}
            sl=addsl(sl,$3->sl); /* signal */
            sl=addtxt(sl," = ");
            sl=addsl(sl,$3->sl); /* signal */
-           sl=addtxt(sl," + 1) begin\n");
+           sl=addtxt(sl," + 1) begin: ");
+           tname_list=blkname_list;
+           sl=addtxt(sl,tname_list->name);
+           blkname_list=blkname_list->next;
+           if (tname_list!=NULL) {
+           free(tname_list->name);
+           free(tname_list);
+           }
+           sl=addtxt(sl,"\n");
            sl=addsl(sl,indents[indent]);
            sl=addsl(sl,$10);   /* a_body:1 */
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"end\n");
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"endgenerate\n");
-           $$=addsl(sl,$16);    /* a_body:2 */
+           $$=addsl(sl,$15);    /* a_body:2 */
          }
-       /* 1       2       3    4 5        6   7     8        9      10      11       12    13     14    15  16 */
-       | optname FOR  signal IN expr DOWNTO expr GENERATE  doindent a_body  unindent END GENERATE oname ';' a_body {
+       /* 1           2       3   4   5    6     7      8        9      10      11       12    13     14    15  16 */
+       | gen_optname FOR  signal IN expr DOWNTO expr generate doindent a_body  unindent endgenerate oname ';' a_body {
          slist *sl;
+           blknamelist* tname_list;
            sl=addsl($1,indents[indent]);
+           sl=addtxt(sl,"genvar ");
+           sl=addsl(sl,$3->sl); /* signal */
+           sl=addtxt(sl,";\n");
+           sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"generate ");
            sl=addtxt(sl,"for (");
            sl=addsl(sl,$3->sl); /* signal */
@@ -1408,11 +1549,21 @@ a_body : rem {$$=addind($1);}
            sl=addsl(sl,$3->sl); /* signal */
            sl=addtxt(sl," = ");
            sl=addsl(sl,$3->sl); /* signal */
-           sl=addtxt(sl," - 1) begin\n");
+           sl=addtxt(sl," - 1) begin: ");
+           tname_list=blkname_list;
+           sl=addtxt(sl,tname_list->name);
+           blkname_list=blkname_list->next;
+           if (tname_list!=NULL) {
+           free(tname_list->name);
+           free(tname_list);
+           }
+           sl=addtxt(sl,"\n");
            sl=addsl(sl,$10);   /* a_body:1 */
            sl=addsl(sl,indents[indent]);
+           sl=addtxt(sl,"end\n");
+           sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"endgenerate\n");
-           $$=addsl(sl,$16);    /* a_body:2 */
+           $$=addsl(sl,$15);    /* a_body:2 */
          }
        ;
 
@@ -1422,25 +1573,32 @@ oname : {$$=NULL;}
 
 optname : rem {$$=$1;}
         | rem NAME ':' {$$=$1; free($2);}
+
+gen_optname : rem {$$=$1;}
+        | rem NAME ':' {
+           blknamelist *tname_list;
+           tname_list = xmalloc (sizeof(blknamelist));
+           tname_list->name = xmalloc(strlen($2));
+           strcpy(tname_list->name, $2);
+           tname_list->next = blkname_list;
+           blkname_list=tname_list;
+           $$=$1;
+           free($2);
+         }
         ;
 
 edge : '(' edge ')' {$$=addwrap("(",$2,")");}
      | NAME '\'' EVENT AND exprc {
-         clkedges[clkptr++]=$5->data.sl->data.txt[0]-'0';
-         assert(clkptr < MAXEDGES);
+         push_clkedge($5->data.sl->data.txt[0]-'0', "name'event and exprc");
        }
      | exprc AND NAME '\'' EVENT {
-         clkedges[clkptr++]=$1->data.sl->data.txt[0]-'0';
-         clkptr++;
-         assert(clkptr < MAXEDGES);
+         push_clkedge($1->data.sl->data.txt[0]-'0', "exprc and name'event");
        }
      | POSEDGE '(' NAME ')' {
-         clkedges[clkptr++]=1;
-         assert(clkptr < MAXEDGES);
+         push_clkedge(1, "explicit");
        }
      | NEGEDGE '(' NAME ')' {
-         clkedges[clkptr++]=0;
-         assert(clkptr < MAXEDGES);
+         push_clkedge(0, "explicit");
        }
      ;
 
@@ -1603,7 +1761,7 @@ p_body : rem {$$=$1;}
            sl=addsl(sl,$3->sl); /* signal */
            sl=addtxt(sl," = ");
            sl=addsl(sl,$3->sl); /* signal */
-           sl=addtxt(sl," + 1) begin \n");
+           sl=addtxt(sl," + 1) begin\n");
            sl=addsl(sl,$10);    /* p_body:1 */
            sl=addsl(sl,indents[indent]);
            sl=addtxt(sl,"end\n");
@@ -1762,9 +1920,9 @@ nodelay  : /* empty */ {delay=0;}
 
 delay    : /* empty */ {$$=0;}
          | AFTER NATURAL NAME {
-                set_timescale($3);
-		$$=$2;
-		}
+             set_timescale($3);
+             $$=$2;
+           }
          ;
 
 map_list : rem map_item {
@@ -1796,6 +1954,12 @@ mvalue : STRING {$$=addvec(NULL,$1);}
        | NATURAL {$$=addval(NULL,$1);}
        | NAME STRING {$$=addvec_base(NULL,$1,$2);}
        | OPEN {$$=addtxt(NULL,"/* open */");}
+       | '(' OTHERS '=' '>' STRING ')' {
+             $$=addtxt(NULL,"{broken{");
+             $$=addtxt($$,$5);
+             $$=addtxt($$,"}}");
+             fprintf(stderr,"Warning on line %d: broken width on port with OTHERS\n",lineno);
+           }
        ;
 
 
@@ -1852,9 +2016,33 @@ signal : NAME {
            ss->sl=sl;
            ss->range=$3;
            if($3->vtype==tVRANGE) {
-             ss->val=1;
+             if (0) {
+               fprintf(stderr,"ss->val set to 1 for ");
+               fslprint(stderr,ss->sl);
+               fprintf(stderr,", why?\n");
+             }
+             ss->val = -1; /* width is in the vrange */
            } else {
+             ss->val = 1;
+           }
+           $$=ss;
+         }
+       | NAME '(' vec_range ')' '(' vec_range ')' {
+         slval *ss;
+         slist *sl;
+           ss=xmalloc(sizeof(slval));
+           sl=addtxt(NULL,$1);
+           sl=addpar_snug2(sl,$3, $6);
+           if(dowith){
+             slwith=sl;
+             dowith=0;
+           }
+           ss->sl=sl;
+           ss->range=$3;
+           if($3->vtype==tVRANGE) {
              ss->val = -1; /* width is in the vrange */
+           } else {
+             ss->val = 1;
            }
            $$=ss;
          }
@@ -1876,6 +2064,12 @@ expr : signal {
            e->sl=addvec(NULL,$1);
            $$=e;
          }
+     | FLOAT {
+         expdata *e=xmalloc(sizeof(expdata));
+           e->op='t'; /* Terminal symbol */
+           e->sl=addtxt(NULL,$1);
+           $$=e;
+         }
      | NATURAL {
          expdata *e=xmalloc(sizeof(expdata));
            e->op='t'; /* Terminal symbol */
@@ -1948,7 +2142,7 @@ expr : signal {
        if ($3->op == 'c') {
          e->sl=addwrap("{",$3->sl,"}");
        } else {
-         e->sl=addwrap("(",$3->sl,")"); 
+         e->sl=addwrap("(",$3->sl,")");
        }
        $$=e;
       }
@@ -2130,27 +2324,27 @@ simple_expr : signal {
        /* one argument type conversion e.g. conv_integer(x) */
        expdata *e;
        e=xmalloc(sizeof(expdata));
-       e->sl=addwrap("(",$3->sl,")"); 
+       e->sl=addwrap("(",$3->sl,")");
        $$=e;
       }
      | '(' simple_expr ')' {
        expdata *e;
        e=xmalloc(sizeof(expdata));
-       e->sl=addwrap("(",$2->sl,")"); 
+       e->sl=addwrap("(",$2->sl,")");
        $$=e;
       }
      ;
 
 %%
 
-char *outfile;    /* Output file */
-char *sourcefile; /* Input file */
+const char *outfile;    /* Output file */
+const char *sourcefile; /* Input file */
 
 int main(int argc, char *argv[]){
 int i,j;
 char *s;
 slist *sl;
-int status; 
+int status;
 
   /* Init the indentation variables */
   indents[0]=NULL;
@@ -2163,13 +2357,26 @@ int status;
     sl->type=1;
     sl->slst=NULL;
   }
-
-  if ((argc>=2) && strcmp(argv[1], "-d") == 0) {
-    yydebug = 1;
-    argv++;
-    argc--;
+  if (argc >= 2 && strcmp(argv[1], "--help") == 0) {
+    printf(
+      "Usage: vhd2vl [-d] [-g1995|-g2001] source_file.vhd > target_file.v\n"
+      "   or  vhd2vl [-d] [-g1995|-g2001] source_file.vhd target_file.v\n");
+    exit(EXIT_SUCCESS);
   }
 
+  while (argc >= 2) {
+     if (strcmp(argv[1], "-d") == 0) {
+       yydebug = 1;
+     } else if (strcmp(argv[1], "-g1995") == 0) {
+       vlog_ver = 0;
+     } else if (strcmp(argv[1], "-g2001") == 0) {
+       vlog_ver = 1;
+     } else {
+       break;
+     }
+     argv++;
+     argc--;
+  }
   if (argc>=2) {
      sourcefile = argv[1];
      if (strcmp(sourcefile,"-")!=0 && !freopen(sourcefile, "r", stdin)) {
@@ -2190,15 +2397,20 @@ int status;
      outfile = "-";
   }
 
-  printf("// File %s translated with vhd2vl v2.3 VHDL to Verilog RTL translator\n\n", sourcefile);
+  printf("// File %s translated with vhd2vl v2.4 VHDL to Verilog RTL translator\n", sourcefile);
+  printf("// vhd2vl settings:\n"
+         "//  * Verilog Module Declaration Style: %s\n\n",
+         vlog_ver ? "2001" : "1995");
   fputs(
 "// vhd2vl is Free (libre) Software:\n"
 "//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd\n"
 "//     http://www.ocean-logic.com\n"
 "//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc\n"
+"//   Modifications (C) 2010 Shankar Giri\n"
 "//   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL\n"
 "//     http://doolittle.icarus.com/~larry/vhd2vl/\n"
-"//\n"
+"//\n", stdout);
+  fputs(
 "//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting\n"
 "//   Verilog for correctness, ideally with a formal verification tool.\n"
 "//\n"
diff --git a/translated_examples/based.v b/translated_examples/based.v
index 7aa61bd..1589453 100644
--- a/translated_examples/based.v
+++ b/translated_examples/based.v
@@ -1,9 +1,12 @@
-// File based.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File based.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index 7fba0eb..c124c42 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -1,9 +1,12 @@
-// File bigfile.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File bigfile.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -237,7 +240,7 @@ wire [31:0] g_dout_i;
       g_n_div_rebeq_dout <= g_n_div_rebeq_dout &  ~g_noop_clr;
       if((g_wrb == 1'b 0)) begin
         // because we now...
-        for (i=0; i <= 1; i = i + 1) begin 
+        for (i=0; i <= 1; i = i + 1) begin
           if((i == 0)) begin
             g_dout_w0x0f_v = g_dout_w0x0f;
           end
@@ -261,7 +264,7 @@ wire [31:0] g_dout_i;
           end
           g_t_u_w0x0f : begin
             // output klim
-            for (j=0; j <= 31; j = j + 1) begin 
+            for (j=0; j <= 31; j = j + 1) begin
               if(((g_t_klim_dout[j] == 1'b 0 && n9_bit_write == 1'b 0) || (din[j] == 1'b 0 && n9_bit_write == 1'b 1))) begin
                 g_t_u_dout[j] <= din[32 * i + j];
               end
@@ -374,7 +377,7 @@ wire [31:0] g_dout_i;
       //  sample
       if((debct_ping == 1'b 1)) begin
         //  taken
-        for (i=0; i <= 3; i = i + 1) begin 
+        for (i=0; i <= 3; i = i + 1) begin
           if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
             q_g_unzq[i] <= 1'b 1;
           end
@@ -389,7 +392,7 @@ wire [31:0] g_dout_i;
         end
       end
       else begin
-        for (i=0; i <= 3; i = i + 1) begin 
+        for (i=0; i <= 3; i = i + 1) begin
           if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
             q_g_unzq[i] <= 1'b 1;
           end
@@ -424,7 +427,7 @@ wire [31:0] g_dout_i;
       g_n_vfr_dout <= {32{1'b0}};
       gwerth <= {32{1'b0}};
     end else begin
-      for (i=0; i <= 31; i = i + 1) begin 
+      for (i=0; i <= 31; i = i + 1) begin
         //  lqq
         //  vfr  matches
         if((g_n_active[i] == 1'b 1)) begin
@@ -464,7 +467,7 @@ wire [31:0] g_dout_i;
   always @(g_n_r_bne_dout or g_e_n_r_dout) begin : P1
     reg [31:0] imod8, idiv8;
 
-    for (i=0; i <= 31; i = i + 1) begin 
+    for (i=0; i <= 31; i = i + 1) begin
       imod8 = i % 8;
       idiv8 = i / 8;
       if((g_n_r_bne_dout == 1'b 0)) begin
@@ -487,7 +490,7 @@ wire [31:0] g_dout_i;
   // Qaz
   assign g_noop = g_n_div_rebeq_dout;
   always @(swe_ed or swe_lv or g_e_z_dout) begin
-    for (i=0; i <= 31; i = i + 1) begin 
+    for (i=0; i <= 31; i = i + 1) begin
       if((g_e_z_dout[i] == 1'b 1)) begin
         swe_qaz1[i] <= swe_ed;
       end
diff --git a/translated_examples/clk.v b/translated_examples/clk.v
index 0f64ee0..b7e1571 100644
--- a/translated_examples/clk.v
+++ b/translated_examples/clk.v
@@ -1,9 +1,12 @@
-// File clk.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File clk.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
diff --git a/translated_examples/counters.v b/translated_examples/counters.v
index 84e1944..277e707 100644
--- a/translated_examples/counters.v
+++ b/translated_examples/counters.v
@@ -1,9 +1,12 @@
-// File counters.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File counters.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index d89ee1f..4d66026 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -1,9 +1,12 @@
-// File expr.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File expr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
diff --git a/translated_examples/for.v b/translated_examples/for.v
index a4d26f2..1c47083 100644
--- a/translated_examples/for.v
+++ b/translated_examples/for.v
@@ -1,9 +1,12 @@
-// File for.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File for.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -46,7 +49,7 @@ reg [6:0] egg_timer;
       //  pulse only lasts for once cycle
       selection <= 1'b 0;
       egg_timer <= {7{1'b1}};
-      for (i=0; i <= j * k; i = i + 1) begin 
+      for (i=0; i <= j * k; i = i + 1) begin
         a = a + i;
         for (k=a - 9; k >=  -14; k = k - 1) begin
           zz5 = zz[31 + k:k];
diff --git a/translated_examples/generate.v b/translated_examples/generate.v
index b2c167e..9dcdf2b 100644
--- a/translated_examples/generate.v
+++ b/translated_examples/generate.v
@@ -1,9 +1,12 @@
-// File generate.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File generate.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -47,7 +50,7 @@ reg [bus_width * 2:0] regSelect;
   // Type   : RW
   //---------------------------------------------------
   genvar bitnum;
-  generate for (bitnum=0; bitnum <= bus_width; bitnum = bitnum + 1) begin
+  generate for (bitnum=0; bitnum <= bus_width; bitnum = bitnum + 1) begin: reg_gp2
       wbit1 wbit1_inst(
           .clk(sysclk),
       .wrb(wrb),
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index 2a47dd3..c5cf39f 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -1,9 +1,12 @@
-// File generic.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File generic.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -55,8 +58,8 @@ wire [31:0] complex;
     case(foo[2:0])
       3'b 000,3'b 110 : code[9:2] <= {3'b 110,egg[325:329]};
       3'b 101 : code[9:2] <= 8'b 11100010;
-      3'b 010 : code[9:2] <= {1{1'b1}};
-      3'b 011 : code[9:2] <= {1{1'b0}};
+      3'b 010 : code[9:2] <= {8{1'b1}};
+      3'b 011 : code[9:2] <= {8{1'b0}};
       default : code[9:2] <= a + b + 1'b 1;
     endcase
   end
diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index 81d006e..f66d2f8 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -1,9 +1,12 @@
-// File genericmap.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File genericmap.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index 9c500e6..cb358a7 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -1,9 +1,12 @@
-// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -16,23 +19,23 @@
 // The result of translation follows.  Its copyright status should be
 // considered unchanged from the original VHDL.
 
-//-------------------------------------------------------------------

-//	Filename:	gh_fifo_async16_sr.vhd

-//

-//			

-//	Description:

-//		an Asynchronous FIFO 

-//              

-//	Copyright (c) 2006 by George Huber 

-//		an OpenCores.org Project

-//		free to use, but see documentation for conditions 								 

-//

-//	Revision	History:

-//	Revision	Date      	Author   	Comment

-//	--------	----------	---------	-----------

-//	1.0     	12/17/06  	h lefevre	Initial revision

-//	

-//------------------------------------------------------

+//-------------------------------------------------------------------
+//	Filename:	gh_fifo_async16_sr.vhd
+//
+//			
+//	Description:
+//		an Asynchronous FIFO 
+//              
+//	Copyright (c) 2006 by George Huber 
+//		an OpenCores.org Project
+//		free to use, but see documentation for conditions 								 
+//
+//	Revision	History:
+//	Revision	Date      	Author   	Comment
+//	--------	----------	---------	-----------
+//	1.0     	12/17/06  	h lefevre	Initial revision
+//	
+//------------------------------------------------------
 // no timescale needed
 
 module gh_fifo_async16_sr(
@@ -49,19 +52,19 @@ full
 );
 
 parameter [31:0] data_width=8;
-// size of data bus

+// size of data bus
 input clk_WR;
-// write clock

+// write clock
 input clk_RD;
-// read clock

+// read clock
 input rst;
-// resets counters

+// resets counters
 input srst;
-// resets counters (sync with clk_WR)

+// resets counters (sync with clk_WR)
 input WR;
-// write control 

+// write control 
 input RD;
-// read control

+// read control
 input [data_width - 1:0] D;
 output [data_width - 1:0] Q;
 output empty;
@@ -84,24 +87,24 @@ reg [data_width - 1:0] ram_mem[15:0];
 wire iempty;
 wire ifull;
 wire add_WR_CE;
-reg [4:0] add_WR;  // 4 bits are used to address MEM

-reg [4:0] add_WR_GC;  // 5 bits are used to compare

-wire [4:0] n_add_WR;  //   for empty, full flags

-reg [4:0] add_WR_RS;  // synced to read clk

+reg [4:0] add_WR;  // 4 bits are used to address MEM
+reg [4:0] add_WR_GC;  // 5 bits are used to compare
+wire [4:0] n_add_WR;  //   for empty, full flags
+reg [4:0] add_WR_RS;  // synced to read clk
 wire add_RD_CE;
 reg [4:0] add_RD;
 reg [4:0] add_RD_GC;
 reg [4:0] add_RD_GCwc;
 wire [4:0] n_add_RD;
-reg [4:0] add_RD_WS;  // synced to write clk

+reg [4:0] add_RD_WS;  // synced to write clk
 reg srst_w;
 reg isrst_w;
 reg srst_r;
 reg isrst_r;
 
-  //------------------------------------------

-  //----- memory -----------------------------

-  //------------------------------------------

+  //------------------------------------------
+  //----- memory -----------------------------
+  //------------------------------------------
   always @(posedge clk_WR) begin
     if(((WR == 1'b 1) && (ifull == 1'b 0))) begin
       ram_mem[(add_WR[3:0])] <= D;
@@ -109,9 +112,9 @@ reg isrst_r;
   end
 
   assign Q = ram_mem[(add_RD[3:0])];
-  //---------------------------------------

-  //--- Write address counter -------------

-  //---------------------------------------

+  //---------------------------------------
+  //--- Write address counter -------------
+  //---------------------------------------
   assign add_WR_CE = (ifull == 1'b 1) ? 1'b 0 : (WR == 1'b 0) ? 1'b 0 : 1'b 1;
   assign n_add_WR = add_WR + 4'h 1;
   always @(posedge clk_WR or posedge rst) begin
@@ -142,9 +145,9 @@ reg isrst_r;
 
   assign full = ifull;
   assign ifull = (iempty == 1'b 1) ? 1'b 0 : (add_RD_WS != add_WR_GC) ? 1'b 0 : 1'b 1;
-  //---------------------------------------

-  //--- Read address counter --------------

-  //---------------------------------------

+  //---------------------------------------
+  //--- Read address counter --------------
+  //---------------------------------------
   assign add_RD_CE = (iempty == 1'b 1) ? 1'b 0 : (RD == 1'b 0) ? 1'b 0 : 1'b 1;
   assign n_add_RD = add_RD + 4'h 1;
   always @(posedge clk_RD or posedge rst) begin
@@ -183,11 +186,11 @@ reg isrst_r;
 
   assign empty = iempty;
   assign iempty = (add_WR_RS == add_RD_GC) ? 1'b 1 : 1'b 0;
-  //--------------------------------

-  //-	sync rest stuff --------------

-  //- srst is sync with clk_WR -----

-  //- srst_r is sync with clk_RD ---

-  //--------------------------------

+  //--------------------------------
+  //-	sync rest stuff --------------
+  //- srst is sync with clk_WR -----
+  //- srst_r is sync with clk_RD ---
+  //--------------------------------
   always @(posedge clk_WR or posedge rst) begin
     if((rst == 1'b 1)) begin
       srst_w <= 1'b 0;
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index 5e30602..459c0ed 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -1,9 +1,12 @@
-// File ifchain.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File ifchain.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -29,13 +32,16 @@ wire clk;
 wire rstn;
 
 
+
 wire [3:0] a;
 wire [3:0] b;
 reg status;
+reg [31:0] c[3:0];
 
   always @(posedge clk) begin
     if({b[1],a[3:2]} == 3'b 001) begin
       status <= 1'b 1;
+      c[0] <= 16'h FFFF;
     end
   end
 
diff --git a/translated_examples/test.v b/translated_examples/test.v
index ff32482..d11e643 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -1,9 +1,12 @@
-// File test.vhd translated with vhd2vl v2.3 VHDL to Verilog RTL translator
+// File test.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
 
 // vhd2vl is Free (libre) Software:
 //   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
 //     http://www.ocean-logic.com
 //   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
 //   Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
 //     http://doolittle.icarus.com/~larry/vhd2vl/
 //
@@ -182,8 +185,8 @@ reg [1:0] colour;
     case(memaddr[2:0])
       3'b 000,3'b 110 : code[9:2] <= {3'b 110,pack[6:2]};
       3'b 101 : code[9:2] <= 8'b 11100010;
-      3'b 010 : code[9:2] <= {1{1'b1}};
-      3'b 011 : code[9:2] <= {1{1'b0}};
+      3'b 010 : code[9:2] <= {8{1'b1}};
+      3'b 011 : code[9:2] <= {8{1'b0}};
       default : code[9:2] <= a + b + 1'b 1;
     endcase
   end