Space deleted in the <size>'<radix><number> notation

It seems to be the more common approach and the VHDL notation BASE#NUMBER#
is translated without spaces. On the other hand, the space gives an error
with Yosys synthesizer.
Files on translated_examples were modified.

14 files changed, 252 insertions, 250 deletions

diff --git a/.gitignore b/.gitignore
index d7bde97..c8dd9c9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,5 @@
 temp
+ignore
 
 src/*.c
 src/*.h
diff --git a/Makefile b/Makefile
index fef4665..e01e53d 100644
--- a/Makefile
+++ b/Makefile
@@ -14,4 +14,5 @@ diff: translate
 	@diff -u translated_examples temp/verilog
 
 clean:
+	make -C src clean
 	rm -fr temp
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index afe5917..9847f4a 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -203,18 +203,18 @@ slist *addsl(slist *sl, slist *sl2){
 
 slist *addvec(slist *sl, char *s){
   sl=addval(sl,strlen(s));
-  sl=addtxt(sl,"'b ");
+  sl=addtxt(sl,"'b");
   sl=addtxt(sl,s);
   return sl;
 }
 
 slist *addvec_base(slist *sl, char *b, char *s){
-  const char *base_str="'b ";
+  const char *base_str="'b";
   int base_mult=1;
   if (strcasecmp(b,"X") == 0) {
-     base_str="'h "; base_mult=4;
+     base_str="'h"; base_mult=4;
   } else if (strcasecmp(b,"O") == 0) {
-     base_str="'o "; base_mult=3;
+     base_str="'o"; base_mult=3;
   } else {
      fprintf(stderr,"Warning on line %d: NAME STRING rule matched but "
        "NAME='%s' is not X or O.\n",lineno, b);
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index 4fee00f..5aaf578 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -113,30 +113,30 @@ reg [31:0] swe_qaz1;
 
 // IMPLEMENTATION
 // constants 
-parameter g_t_klim_w0x0f = 5'b 00000;
-parameter g_t_u_w0x0f = 5'b 00001;
-parameter g_t_l_w0x0f = 5'b 00010;
-parameter g_t_hhh_l_w0x0f = 5'b 00011;
-parameter g_t_jkl_sink_l_w0x0f = 5'b 00100;
-parameter g_secondary_t_l_w0x0f = 5'b 00101;
-parameter g_style_c_l_w0x0f = 5'b 00110;
-parameter g_e_z_w0x0f = 5'b 00111;
-parameter g_n_both_qbars_l_w0x0f = 5'b 01000;
-parameter g_style_vfr_w0x0f = 5'b 01001;
-parameter g_style_klim_w0x0f = 5'b 01010;
-parameter g_unklimed_style_vfr_w0x0f = 5'b 01011;
-parameter g_style_t_y_w0x0f = 5'b 01100;
-parameter g_n_l_w0x0f = 5'b 01101;
-parameter g_n_vfr_w0x0f = 5'b 01110;
-parameter g_e_n_r_w0x0f = 5'b 01111;
-parameter g_n_r_bne_w0x0f = 5'b 10000;
-parameter g_n_div_rebeq_w0x0f = 5'b 10001;
-parameter g_alu_l_w0x0f = 5'b 10010;
-parameter g_t_qaz_mult_low_w0x0f = 5'b 10011;
-parameter g_t_qaz_mult_high_w0x0f = 5'b 10100;
-parameter gwerthernal_style_u_w0x0f = 5'b 10101;
-parameter gwerthernal_style_l_w0x0f = 5'b 10110;
-parameter g_style_main_reset_hold_w0x0f = 5'b 10111;  // comment
+parameter g_t_klim_w0x0f = 5'b00000;
+parameter g_t_u_w0x0f = 5'b00001;
+parameter g_t_l_w0x0f = 5'b00010;
+parameter g_t_hhh_l_w0x0f = 5'b00011;
+parameter g_t_jkl_sink_l_w0x0f = 5'b00100;
+parameter g_secondary_t_l_w0x0f = 5'b00101;
+parameter g_style_c_l_w0x0f = 5'b00110;
+parameter g_e_z_w0x0f = 5'b00111;
+parameter g_n_both_qbars_l_w0x0f = 5'b01000;
+parameter g_style_vfr_w0x0f = 5'b01001;
+parameter g_style_klim_w0x0f = 5'b01010;
+parameter g_unklimed_style_vfr_w0x0f = 5'b01011;
+parameter g_style_t_y_w0x0f = 5'b01100;
+parameter g_n_l_w0x0f = 5'b01101;
+parameter g_n_vfr_w0x0f = 5'b01110;
+parameter g_e_n_r_w0x0f = 5'b01111;
+parameter g_n_r_bne_w0x0f = 5'b10000;
+parameter g_n_div_rebeq_w0x0f = 5'b10001;
+parameter g_alu_l_w0x0f = 5'b10010;
+parameter g_t_qaz_mult_low_w0x0f = 5'b10011;
+parameter g_t_qaz_mult_high_w0x0f = 5'b10100;
+parameter gwerthernal_style_u_w0x0f = 5'b10101;
+parameter gwerthernal_style_l_w0x0f = 5'b10110;
+parameter g_style_main_reset_hold_w0x0f = 5'b10111;  // comment
 reg [31:0] g_t_klim_dout;
 reg [31:0] g_t_u_dout;
 reg [31:0] g_t_l_dout;
@@ -185,18 +185,18 @@ wire [31:0] g_dout_i;
   assign g_zaq_ctl_i =  ~((((g_t_l_dout &  ~g_t_jkl_sink_l_dout)) | ((g_t_l_dout & g_t_jkl_sink_l_dout &  ~g_zaq_out_i))));
   // mux
   //vnavigatoroff
-  assign g_zaq_ctl = scanb == 1'b 1 ? g_zaq_ctl_i : 32'b 00000000000000000000000000000000;
+  assign g_zaq_ctl = scanb == 1'b1 ? g_zaq_ctl_i : 32'b00000000000000000000000000000000;
   //vnavigatoron
   assign g_zaq_hhh_enb =  ~((g_t_hhh_l_dout));
   assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout;
   assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout;
   // Dout
-  assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b 0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b 0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b 00000000000000000000000000000000;
-  assign g_dout = g_rdb == 1'b 0 ? g_dout_i : {32{1'b1}};
+  assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b00000000000000000000000000000000;
+  assign g_dout = g_rdb == 1'b0 ? g_dout_i : {32{1'b1}};
   // this  can be used to use zzz1
   always @(posedge sysclk) begin
-    if((scanb == 1'b 1)) begin
-      if((reset == 1'b 1)) begin
+    if((scanb == 1'b1)) begin
+      if((reset == 1'b1)) begin
         g_style_main_reset_hold_dout <= g_zaq_in;
       end
       //vnavigatoroff
@@ -213,7 +213,7 @@ wire [31:0] g_dout_i;
   always @(posedge reset or posedge sysclk) begin : P2
     reg [4:0] g_dout_w0x0f_v;
 
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       g_t_klim_dout <= {32{1'b0}};
       g_t_u_dout <= {32{1'b0}};
       g_t_l_dout <= {32{1'b0}};
@@ -227,7 +227,7 @@ wire [31:0] g_dout_i;
       g_style_t_y_dout <= {32{1'b0}};
       g_n_l_dout <= {32{1'b0}};
       g_e_n_r_dout <= {32{1'b0}};
-      g_n_r_bne_dout <= 1'b 0;
+      g_n_r_bne_dout <= 1'b0;
       g_n_div_rebeq_dout <= {32{1'b1}};
       g_alu_l_dout <= {32{1'b0}};
       g_t_qaz_mult_low_dout <= {32{1'b1}};
@@ -238,16 +238,16 @@ wire [31:0] g_dout_i;
     end else begin
       // clear
       g_n_div_rebeq_dout <= g_n_div_rebeq_dout &  ~g_noop_clr;
-      if((g_wrb == 1'b 0)) begin
+      if((g_wrb == 1'b0)) begin
         // because we now...
         for (i=0; i <= 1; i = i + 1) begin
           if((i == 0)) begin
             g_dout_w0x0f_v = g_dout_w0x0f;
           end
           else if((i == 1)) begin
-            if((n9_bit_write == 1'b 1)) begin
+            if((n9_bit_write == 1'b1)) begin
               // set
-              g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b 1};
+              g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b1};
             end
             else begin
               disable;  //VHD2VL: add block name here
@@ -265,7 +265,7 @@ wire [31:0] g_dout_i;
           g_t_u_w0x0f : begin
             // output klim
             for (j=0; j <= 31; j = j + 1) begin
-              if(((g_t_klim_dout[j] == 1'b 0 && n9_bit_write == 1'b 0) || (din[j] == 1'b 0 && n9_bit_write == 1'b 1))) begin
+              if(((g_t_klim_dout[j] == 1'b0 && n9_bit_write == 1'b0) || (din[j] == 1'b0 && n9_bit_write == 1'b1))) begin
                 g_t_u_dout[j] <= din[32 * i + j];
               end
             end
@@ -346,7 +346,7 @@ wire [31:0] g_dout_i;
 
   // sample
   always @(posedge reset or posedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       q_g_zaq_in <= {32{1'b0}};
       q2_g_zaq_in <= {32{1'b0}};
       q3_g_zaq_in <= {32{1'b0}};
@@ -364,29 +364,29 @@ wire [31:0] g_dout_i;
   // qaz
   assign g_style_vfr_dout = {g_zaq_in_y[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])))};
   // in scan mode
-  assign g_zaq_in_y_no_dout = scanb == 1'b 1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout;
+  assign g_zaq_in_y_no_dout = scanb == 1'b1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout;
   //vnavigatoron
   assign g_sys_in_i = ({g_zaq_in_y_no_dout[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])))});
   assign g_sys_in_ii = ((g_sys_in_i &  ~gwerthernal_style_l_dout)) | ((gwerthernal_style_u_dout & gwerthernal_style_l_dout));
   assign g_sys_in = g_sys_in_ii;
   always @(posedge reset or posedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       q_g_zaq_in_cd <= {4{1'b0}};
       q_g_unzq <= {4{1'b1}};
     end else begin
       //  sample
-      if((debct_ping == 1'b 1)) begin
+      if((debct_ping == 1'b1)) begin
         //  taken
         for (i=0; i <= 3; i = i + 1) begin
           if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
-            q_g_unzq[i] <= 1'b 1;
+            q_g_unzq[i] <= 1'b1;
           end
           else begin
-            if((q_g_unzq[i] == 1'b 0)) begin
+            if((q_g_unzq[i] == 1'b0)) begin
               q_g_zaq_in_cd[i] <= g_zaq_in_y[i];
             end
             else begin
-              q_g_unzq[i] <= 1'b 0;
+              q_g_unzq[i] <= 1'b0;
             end
           end
         end
@@ -394,7 +394,7 @@ wire [31:0] g_dout_i;
       else begin
         for (i=0; i <= 3; i = i + 1) begin
           if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
-            q_g_unzq[i] <= 1'b 1;
+            q_g_unzq[i] <= 1'b1;
           end
         end
       end
@@ -403,16 +403,16 @@ wire [31:0] g_dout_i;
 
   // generate lqqs 
   always @(posedge reset or posedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       q_g_style_vfr_dout <= {32{1'b0}};
     end else begin
-      if((scanb == 1'b 1)) begin
+      if((scanb == 1'b1)) begin
         q_g_style_vfr_dout <= g_style_vfr_dout;
         //vnavigatoroff
       end
       else begin
         // in scan 
-        q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b 0,g_zaq_out_i[15:1],1'b 0}) | g_zaq_ctl_i | g_sys_in_ii;
+        q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b0,g_zaq_out_i[15:1],1'b0}) | g_zaq_ctl_i | g_sys_in_ii;
       end
       //vnavigatoron
     end
@@ -423,18 +423,18 @@ wire [31:0] g_dout_i;
   // check for lqq active and set lqq vfr register
   // also clear
   always @(posedge reset or posedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       g_n_vfr_dout <= {32{1'b0}};
       gwerth <= {32{1'b0}};
     end else begin
       for (i=0; i <= 31; i = i + 1) begin
         //  lqq
         //  vfr  matches
-        if((g_n_active[i] == 1'b 1)) begin
-          gwerth[i] <= 1'b 1;
-          if((g_e_z_dout[i] == 1'b 1)) begin
+        if((g_n_active[i] == 1'b1)) begin
+          gwerth[i] <= 1'b1;
+          if((g_e_z_dout[i] == 1'b1)) begin
             //  lqq          
-            g_n_vfr_dout[i] <= 1'b 1;
+            g_n_vfr_dout[i] <= 1'b1;
           end
           else begin
             g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
@@ -442,19 +442,19 @@ wire [31:0] g_dout_i;
         end
         else begin
           //  clear
-          if((g_e_z_dout[i] == 1'b 0)) begin
+          if((g_e_z_dout[i] == 1'b0)) begin
             g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
             // default always assign
             // in both
-            if((g_n_both_qbars_l_dout[i] == 1'b 1 || g_style_vfr_dout[i] == 1'b 1)) begin
-              gwerth[i] <= 1'b 0;
+            if((g_n_both_qbars_l_dout[i] == 1'b1 || g_style_vfr_dout[i] == 1'b1)) begin
+              gwerth[i] <= 1'b0;
             end
           end
           else begin
             // write
-            if((g_wrb == 1'b 0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b 1)) begin
-              gwerth[i] <= 1'b 0;
-              g_n_vfr_dout[i] <= 1'b 0;
+            if((g_wrb == 1'b0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b1)) begin
+              gwerth[i] <= 1'b0;
+              g_n_vfr_dout[i] <= 1'b0;
             end
           end
         end
@@ -470,7 +470,7 @@ wire [31:0] g_dout_i;
     for (i=0; i <= 31; i = i + 1) begin
       imod8 = i % 8;
       idiv8 = i / 8;
-      if((g_n_r_bne_dout == 1'b 0)) begin
+      if((g_n_r_bne_dout == 1'b0)) begin
         // non-unique
         g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
       end
@@ -491,7 +491,7 @@ wire [31:0] g_dout_i;
   assign g_noop = g_n_div_rebeq_dout;
   always @(swe_ed or swe_lv or g_e_z_dout) begin
     for (i=0; i <= 31; i = i + 1) begin
-      if((g_e_z_dout[i] == 1'b 1)) begin
+      if((g_e_z_dout[i] == 1'b1)) begin
         swe_qaz1[i] <= swe_ed;
       end
       else begin
diff --git a/translated_examples/clk.v b/translated_examples/clk.v
index 41797b7..faf911c 100644
--- a/translated_examples/clk.v
+++ b/translated_examples/clk.v
@@ -48,7 +48,7 @@ reg [2:0] baz;
 reg [4:7 - 1] egg;
 
   always @(posedge reset or posedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       foo <= {(((10 + 3))-((0))+1){1'b1}};
     end else begin
       foo <= ival[31:31 - ((10 + 3))];
@@ -56,7 +56,7 @@ reg [4:7 - 1] egg;
   end
 
   always @(negedge preset or negedge dsysclk) begin
-    if((preset != 1'b 1)) begin
+    if((preset != 1'b1)) begin
       baz <= {3{1'b0}};
     end else begin
       baz <= ival[2:0];
@@ -64,7 +64,7 @@ reg [4:7 - 1] egg;
   end
 
   always @(negedge qreset or negedge esysclk) begin
-    if((qreset != 1'b 1)) begin
+    if((qreset != 1'b1)) begin
       egg <= {(((7 - 1))-((4))+1){1'b0}};
     end else begin
       egg <= ival[6:4];
diff --git a/translated_examples/counters.v b/translated_examples/counters.v
index 23fc54a..28d0ad2 100644
--- a/translated_examples/counters.v
+++ b/translated_examples/counters.v
@@ -200,92 +200,92 @@ reg prev_do_file_card;
   assign debct_cwm = debct_cwm_i;
   assign wdfilecardA2P = do_file_card_i;
   always @(posedge foo_card or posedge sysclk) begin
-    if(foo_card == 1'b 1) begin
+    if(foo_card == 1'b1) begin
       wfoo0_llwln_var <= {32{1'b0}};
       debct_var <= {32{1'b0}};
       Z0_var <= {32{1'b0}};
       Y1_var <= {32{1'b0}};
       X2_var <= {32{1'b0}};
       W3_var <= {32{1'b0}};
-      wfoo0_cwm <= 1'b 0;
-      debct_cwm_i <= 1'b 0;
-      debct_pull <= 1'b 0;
-      Z0_cwm_i <= 1'b 0;
-      Y1_cwm_i <= 1'b 0;
-      X2_cwm_i <= 1'b 0;
-      W3_cwm_i <= 1'b 0;
-      main_wfoo0_cwm <= 1'b 0;
-      file_card_i <= 1'b 0;
-      do_q3p_wfoo0 <= 1'b 0;
-      do_file_card_i <= 1'b 0;
-      prev_do_file_card <= 1'b 0;
-      do_q3p_Z0 <= 1'b 0;
-      do_q3p_Y1 <= 1'b 0;
-      do_q3p_X2 <= 1'b 0;
-      do_q3p_W3 <= 1'b 0;
-      do_q3p_debct <= 1'b 0;
+      wfoo0_cwm <= 1'b0;
+      debct_cwm_i <= 1'b0;
+      debct_pull <= 1'b0;
+      Z0_cwm_i <= 1'b0;
+      Y1_cwm_i <= 1'b0;
+      X2_cwm_i <= 1'b0;
+      W3_cwm_i <= 1'b0;
+      main_wfoo0_cwm <= 1'b0;
+      file_card_i <= 1'b0;
+      do_q3p_wfoo0 <= 1'b0;
+      do_file_card_i <= 1'b0;
+      prev_do_file_card <= 1'b0;
+      do_q3p_Z0 <= 1'b0;
+      do_q3p_Y1 <= 1'b0;
+      do_q3p_X2 <= 1'b0;
+      do_q3p_W3 <= 1'b0;
+      do_q3p_debct <= 1'b0;
     end else begin
       // pull
-      debct_pull <= 1'b 0;
-      do_file_card_i <= 1'b 0;
+      debct_pull <= 1'b0;
+      do_file_card_i <= 1'b0;
       //--
       //  wfoo0
-      if(wfoo0_baz == 1'b 1) begin
+      if(wfoo0_baz == 1'b1) begin
         wfoo0_llwln_var <= (wfoo0_turn);
-        main_wfoo0_cwm <= 1'b 0;
-        if(wfoo0_llwln_var == 32'b 00000000000000000000000000000000) begin
-          do_q3p_wfoo0 <= 1'b 0;
+        main_wfoo0_cwm <= 1'b0;
+        if(wfoo0_llwln_var == 32'b00000000000000000000000000000000) begin
+          do_q3p_wfoo0 <= 1'b0;
         end
         else begin
-          do_q3p_wfoo0 <= 1'b 1;
+          do_q3p_wfoo0 <= 1'b1;
         end
       end
       else begin
-        if(do_q3p_wfoo0 == 1'b 1 && wfoo0_blrb == 1'b 1) begin
+        if(do_q3p_wfoo0 == 1'b1 && wfoo0_blrb == 1'b1) begin
           wfoo0_llwln_var <= wfoo0_llwln_var - 1;
-          if((wfoo0_llwln_var == 32'b 00000000000000000000000000000000)) begin
+          if((wfoo0_llwln_var == 32'b00000000000000000000000000000000)) begin
             wfoo0_llwln_var <= (wfoo0_turn);
-            if(main_wfoo0_cwm == 1'b 0) begin
-              wfoo0_cwm <= 1'b 1;
-              main_wfoo0_cwm <= 1'b 1;
+            if(main_wfoo0_cwm == 1'b0) begin
+              wfoo0_cwm <= 1'b1;
+              main_wfoo0_cwm <= 1'b1;
             end
             else begin
-              do_file_card_i <= 1'b 1;
-              do_q3p_wfoo0 <= 1'b 0;
+              do_file_card_i <= 1'b1;
+              do_q3p_wfoo0 <= 1'b0;
             end
           end
         end
       end
-      if(wfoo0_zz1pb == 1'b 0) begin
-        wfoo0_cwm <= 1'b 0;
+      if(wfoo0_zz1pb == 1'b0) begin
+        wfoo0_cwm <= 1'b0;
       end
-      if(Z0_baz == 1'b 1) begin
+      if(Z0_baz == 1'b1) begin
         // counter Baz
         Z0_var <= (Z0_turn);
-        if(Z0_turn == 32'b 00000000000000000000000000000000) begin
-          do_q3p_Z0 <= 1'b 0;
+        if(Z0_turn == 32'b00000000000000000000000000000000) begin
+          do_q3p_Z0 <= 1'b0;
         end
         else begin
-          do_q3p_Z0 <= 1'b 1;
+          do_q3p_Z0 <= 1'b1;
         end
       end
       else begin
-        if(do_q3p_Z0 == 1'b 1 && Z0_blrb == 1'b 1) begin
-          if(Z0_bar == 1'b 0) begin
-            if(Z0_cwm_i == 1'b 0) begin
-              if(do_q3p_Z0 == 1'b 1) begin
+        if(do_q3p_Z0 == 1'b1 && Z0_blrb == 1'b1) begin
+          if(Z0_bar == 1'b0) begin
+            if(Z0_cwm_i == 1'b0) begin
+              if(do_q3p_Z0 == 1'b1) begin
                 Z0_var <= Z0_var - 1;
-                if((Z0_var == 32'b 00000000000000000000000000000001)) begin
-                  Z0_cwm_i <= 1'b 1;
-                  do_q3p_Z0 <= 1'b 0;
+                if((Z0_var == 32'b00000000000000000000000000000001)) begin
+                  Z0_cwm_i <= 1'b1;
+                  do_q3p_Z0 <= 1'b0;
                 end
               end
             end
           end
           else begin
             Z0_var <= Z0_var - 1;
-            if((Z0_var == 32'b 00000000000000000000000000000000)) begin
-              Z0_cwm_i <= 1'b 1;
+            if((Z0_var == 32'b00000000000000000000000000000000)) begin
+              Z0_cwm_i <= 1'b1;
               Z0_var <= (Z0_turn);
             end
           end
@@ -293,135 +293,135 @@ reg prev_do_file_card;
         end
       end
       // Z0_blrb
-      if(Z0_zz1pb == 1'b 0) begin
-        Z0_cwm_i <= 1'b 0;
+      if(Z0_zz1pb == 1'b0) begin
+        Z0_cwm_i <= 1'b0;
       end
-      if(Y1_baz == 1'b 1) begin
+      if(Y1_baz == 1'b1) begin
         // counter Baz
         Y1_var <= (Y1_turn);
-        if(Y1_turn == 32'b 00000000000000000000000000000000) begin
-          do_q3p_Y1 <= 1'b 0;
+        if(Y1_turn == 32'b00000000000000000000000000000000) begin
+          do_q3p_Y1 <= 1'b0;
         end
         else begin
-          do_q3p_Y1 <= 1'b 1;
+          do_q3p_Y1 <= 1'b1;
         end
       end
-      else if(do_q3p_Y1 == 1'b 1 && Y1_blrb == 1'b 1) begin
-        if(Y1_bar == 1'b 0) begin
-          if(Y1_cwm_i == 1'b 0) begin
-            if(do_q3p_Y1 == 1'b 1) begin
+      else if(do_q3p_Y1 == 1'b1 && Y1_blrb == 1'b1) begin
+        if(Y1_bar == 1'b0) begin
+          if(Y1_cwm_i == 1'b0) begin
+            if(do_q3p_Y1 == 1'b1) begin
               Y1_var <= Y1_var - 1;
-              if((Y1_var == 32'b 00000000000000000000000000000001)) begin
-                Y1_cwm_i <= 1'b 1;
-                do_q3p_Y1 <= 1'b 0;
+              if((Y1_var == 32'b00000000000000000000000000000001)) begin
+                Y1_cwm_i <= 1'b1;
+                do_q3p_Y1 <= 1'b0;
               end
             end
           end
         end
         else begin
           Y1_var <= Y1_var - 1;
-          if((Y1_var == 32'b 00000000000000000000000000000000)) begin
-            Y1_cwm_i <= 1'b 1;
+          if((Y1_var == 32'b00000000000000000000000000000000)) begin
+            Y1_cwm_i <= 1'b1;
             Y1_var <= (Y1_turn);
           end
         end
         // Y1_bar
       end
       // Y1_blrb
-      if(Y1_zz1pb == 1'b 0) begin
-        Y1_cwm_i <= 1'b 0;
+      if(Y1_zz1pb == 1'b0) begin
+        Y1_cwm_i <= 1'b0;
       end
-      if(X2_baz == 1'b 1) begin
+      if(X2_baz == 1'b1) begin
         // counter Baz
         X2_var <= (X2_turn);
-        if(X2_turn == 32'b 00000000000000000000000000000000) begin
-          do_q3p_X2 <= 1'b 0;
+        if(X2_turn == 32'b00000000000000000000000000000000) begin
+          do_q3p_X2 <= 1'b0;
         end
         else begin
-          do_q3p_X2 <= 1'b 1;
+          do_q3p_X2 <= 1'b1;
         end
       end
-      else if(do_q3p_X2 == 1'b 1 && X2_blrb == 1'b 1) begin
-        if(X2_bar == 1'b 0) begin
-          if(X2_cwm_i == 1'b 0) begin
-            if(do_q3p_X2 == 1'b 1) begin
+      else if(do_q3p_X2 == 1'b1 && X2_blrb == 1'b1) begin
+        if(X2_bar == 1'b0) begin
+          if(X2_cwm_i == 1'b0) begin
+            if(do_q3p_X2 == 1'b1) begin
               X2_var <= X2_var - 1;
-              if((X2_var == 32'b 00000000000000000000000000000001)) begin
-                X2_cwm_i <= 1'b 1;
-                do_q3p_X2 <= 1'b 0;
+              if((X2_var == 32'b00000000000000000000000000000001)) begin
+                X2_cwm_i <= 1'b1;
+                do_q3p_X2 <= 1'b0;
               end
             end
           end
         end
         else begin
           X2_var <= X2_var - 1;
-          if((X2_var == 32'b 00000000000000000000000000000000)) begin
+          if((X2_var == 32'b00000000000000000000000000000000)) begin
             //{
-            X2_cwm_i <= 1'b 1;
+            X2_cwm_i <= 1'b1;
             X2_var <= (X2_turn);
           end
         end
         //X2_bar
       end
       // X2_blrb
-      if(X2_zz1pb == 1'b 0) begin
-        X2_cwm_i <= 1'b 0;
+      if(X2_zz1pb == 1'b0) begin
+        X2_cwm_i <= 1'b0;
       end
-      if(W3_baz == 1'b 1) begin
+      if(W3_baz == 1'b1) begin
         // counter Baz
         W3_var <= (W3_turn);
-        if(W3_turn == 32'b 00000000000000000000000000000000) begin
-          do_q3p_W3 <= 1'b 0;
+        if(W3_turn == 32'b00000000000000000000000000000000) begin
+          do_q3p_W3 <= 1'b0;
         end
         else begin
-          do_q3p_W3 <= 1'b 1;
+          do_q3p_W3 <= 1'b1;
         end
       end
-      else if(do_q3p_W3 == 1'b 1 && W3_blrb == 1'b 1) begin
-        if(W3_bar == 1'b 0) begin
-          if(W3_cwm_i == 1'b 0) begin
-            if(do_q3p_W3 == 1'b 1) begin
+      else if(do_q3p_W3 == 1'b1 && W3_blrb == 1'b1) begin
+        if(W3_bar == 1'b0) begin
+          if(W3_cwm_i == 1'b0) begin
+            if(do_q3p_W3 == 1'b1) begin
               W3_var <= W3_var - 1;
-              if((W3_var == 32'b 00000000000000000000000000000001)) begin
-                W3_cwm_i <= 1'b 1;
-                do_q3p_W3 <= 1'b 0;
+              if((W3_var == 32'b00000000000000000000000000000001)) begin
+                W3_cwm_i <= 1'b1;
+                do_q3p_W3 <= 1'b0;
               end
             end
           end
         end
         else begin
           W3_var <= W3_var - 1;
-          if((W3_var == 32'b 00000000000000000000000000000000)) begin
+          if((W3_var == 32'b00000000000000000000000000000000)) begin
             //{
-            W3_cwm_i <= 1'b 1;
+            W3_cwm_i <= 1'b1;
             W3_var <= (W3_turn);
           end
         end
         // W3_bar
       end
       // W3_blrb
-      if(W3_zz1pb == 1'b 0) begin
-        W3_cwm_i <= 1'b 0;
+      if(W3_zz1pb == 1'b0) begin
+        W3_cwm_i <= 1'b0;
       end
-      if(debct_baz == 1'b 1) begin
+      if(debct_baz == 1'b1) begin
         // counter Baz
         debct_var <= (debct_turn);
-        if(debct_turn == 32'b 00000000000000000000000000000000) begin
-          do_q3p_debct <= 1'b 0;
+        if(debct_turn == 32'b00000000000000000000000000000000) begin
+          do_q3p_debct <= 1'b0;
         end
         else begin
-          do_q3p_debct <= 1'b 1;
+          do_q3p_debct <= 1'b1;
         end
       end
-      else if(do_q3p_debct == 1'b 1 && debct_blrb == 1'b 1) begin
-        if(debct_bar == 1'b 0) begin
-          if(debct_cwm_i == 1'b 0) begin
-            if(do_q3p_debct == 1'b 1) begin
+      else if(do_q3p_debct == 1'b1 && debct_blrb == 1'b1) begin
+        if(debct_bar == 1'b0) begin
+          if(debct_cwm_i == 1'b0) begin
+            if(do_q3p_debct == 1'b1) begin
               debct_var <= debct_var - 1;
-              if((debct_var == 32'b 00000000000000000000000000000001)) begin
-                debct_cwm_i <= 1'b 1;
-                debct_pull <= 1'b 1;
-                do_q3p_debct <= 1'b 0;
+              if((debct_var == 32'b00000000000000000000000000000001)) begin
+                debct_cwm_i <= 1'b1;
+                debct_pull <= 1'b1;
+                do_q3p_debct <= 1'b0;
               end
             end
           end
@@ -431,10 +431,10 @@ reg prev_do_file_card;
           //  Continue
           debct_var <= debct_var - 1;
           // ending
-          if((debct_var == 32'b 00000000000000000000000000000000)) begin
+          if((debct_var == 32'b00000000000000000000000000000000)) begin
             //{
-            debct_cwm_i <= 1'b 1;
-            debct_pull <= 1'b 1;
+            debct_cwm_i <= 1'b1;
+            debct_pull <= 1'b1;
             debct_var <= (debct_turn);
           end
         end
@@ -442,8 +442,8 @@ reg prev_do_file_card;
       end
       // debct_blrb
       // comment
-      if(debct_zz1pb == 1'b 0) begin
-        debct_cwm_i <= 1'b 0;
+      if(debct_zz1pb == 1'b0) begin
+        debct_cwm_i <= 1'b0;
       end
     end
   end
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index 43f6221..dd755b7 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -47,7 +47,7 @@ wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
   assign out_i = ((enable & ((aux ^ outy)))) | ((debug & dv &  ~enable)) | (( ~debug &  ~enable & value));
   // not drive
   always @(negedge reset or negedge sysclk) begin
-    if((reset != 1'b 0)) begin
+    if((reset != 1'b0)) begin
       foo <= {14{1'b0}};
     end else begin
       foo[3 * ((2 - 1))] <= (4 * ((1 + 2)));
diff --git a/translated_examples/for.v b/translated_examples/for.v
index a79e5e1..2eea327 100644
--- a/translated_examples/for.v
+++ b/translated_examples/for.v
@@ -41,13 +41,13 @@ reg [6:0] egg_timer;
     reg [31:0] zz5;
     reg [511:0] zz;
 
-    if(reset == 1'b 1) begin
-      selection <= 1'b 1;
+    if(reset == 1'b1) begin
+      selection <= 1'b1;
       timer_var = 2;
       egg_timer <= {7{1'b0}};
     end else begin
       //  pulse only lasts for once cycle
-      selection <= 1'b 0;
+      selection <= 1'b0;
       egg_timer <= {7{1'b1}};
       for (i=0; i <= j * k; i = i + 1) begin
         a = a + i;
diff --git a/translated_examples/generate.v b/translated_examples/generate.v
index 29fbe5d..25746f9 100644
--- a/translated_examples/generate.v
+++ b/translated_examples/generate.v
@@ -62,7 +62,7 @@ reg [bus_width * 2:0] regSelect;
   end
   endgenerate
   always @(posedge sysclk) begin
-    regSelect[1] <= 1'b 1;
+    regSelect[1] <= 1'b1;
   end
 
 
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index ca6e298..fe2e5c4 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -32,7 +32,7 @@ qtd,
 base
 );
 
-parameter [7:0] dog_width=8'b 10101100;
+parameter [7:0] dog_width=8'b10101100;
 parameter [31:0] bus_width=32;
 input reset, sysclk;
 input [bus_width:0] a, b, enf, load, qtd, base;
@@ -56,11 +56,11 @@ wire [31:0] complex;
   // Example of with statement
   always @(*) begin
     case(foo[2:0])
-      3'b 000,3'b 110 : code[9:2] <= {3'b 110,egg[325:329]};
-      3'b 101 : code[9:2] <= 8'b 11100010;
-      3'b 010 : code[9:2] <= {8{1'b1}};
-      3'b 011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b 1;
+      3'b000,3'b110 : code[9:2] <= {3'b110,egg[325:329]};
+      3'b101 : code[9:2] <= 8'b11100010;
+      3'b010 : code[9:2] <= {8{1'b1}};
+      3'b011 : code[9:2] <= {8{1'b0}};
+      default : code[9:2] <= a + b + 1'b1;
     endcase
   end
 
@@ -68,6 +68,6 @@ wire [31:0] complex;
   assign foo = {(((1 + 1))-((0))+1){1'b0}};
   assign egg = {78{1'b0}};
   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
-  assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001};
+  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
 
 endmodule
diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index 26573b9..7a5da32 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -48,7 +48,7 @@ complex,
 eno
 );
 
-parameter rst_val=1'b 0;
+parameter rst_val=1'b0;
 parameter [31:0] thing_size=201;
 parameter [31:0] bus_width=201 % 32;
 input clk, rstn;
@@ -116,7 +116,7 @@ wire [1:0] colour;
     .memdout(memdout));
 
   dsp #(
-      .rst_val(1'b 1),
+      .rst_val(1'b1),
     .bus_width(16))
   dsp_inst1(
       // Inputs
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index 2f711a9..7128d4e 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -106,7 +106,7 @@ reg isrst_r;
   //----- memory -----------------------------
   //------------------------------------------
   always @(posedge clk_WR) begin
-    if(((WR == 1'b 1) && (ifull == 1'b 0))) begin
+    if(((WR == 1'b1) && (ifull == 1'b0))) begin
       ram_mem[(add_WR[3:0])] <= D;
     end
   end
@@ -115,20 +115,20 @@ reg isrst_r;
   //---------------------------------------
   //--- Write address counter -------------
   //---------------------------------------
-  assign add_WR_CE = (ifull == 1'b 1) ? 1'b 0 : (WR == 1'b 0) ? 1'b 0 : 1'b 1;
-  assign n_add_WR = add_WR + 4'h 1;
+  assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1;
+  assign n_add_WR = add_WR + 4'h1;
   always @(posedge clk_WR or posedge rst) begin
-    if((rst == 1'b 1)) begin
+    if((rst == 1'b1)) begin
       add_WR <= {5{1'b0}};
-      add_RD_WS <= 5'b 11000;
+      add_RD_WS <= 5'b11000;
       add_WR_GC <= {5{1'b0}};
     end else begin
       add_RD_WS <= add_RD_GCwc;
-      if((srst_w == 1'b 1)) begin
+      if((srst_w == 1'b1)) begin
         add_WR <= {5{1'b0}};
         add_WR_GC <= {5{1'b0}};
       end
-      else if((add_WR_CE == 1'b 1)) begin
+      else if((add_WR_CE == 1'b1)) begin
         add_WR <= n_add_WR;
         add_WR_GC[0] <= n_add_WR[0] ^ n_add_WR[1];
         add_WR_GC[1] <= n_add_WR[1] ^ n_add_WR[2];
@@ -144,26 +144,26 @@ reg isrst_r;
   end
 
   assign full = ifull;
-  assign ifull = (iempty == 1'b 1) ? 1'b 0 : (add_RD_WS != add_WR_GC) ? 1'b 0 : 1'b 1;
+  assign ifull = (iempty == 1'b1) ? 1'b0 : (add_RD_WS != add_WR_GC) ? 1'b0 : 1'b1;
   //---------------------------------------
   //--- Read address counter --------------
   //---------------------------------------
-  assign add_RD_CE = (iempty == 1'b 1) ? 1'b 0 : (RD == 1'b 0) ? 1'b 0 : 1'b 1;
-  assign n_add_RD = add_RD + 4'h 1;
+  assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
+  assign n_add_RD = add_RD + 4'h1;
   always @(posedge clk_RD or posedge rst) begin
-    if((rst == 1'b 1)) begin
+    if((rst == 1'b1)) begin
       add_RD <= {5{1'b0}};
       add_WR_RS <= {5{1'b0}};
       add_RD_GC <= {5{1'b0}};
-      add_RD_GCwc <= 5'b 11000;
+      add_RD_GCwc <= 5'b11000;
     end else begin
       add_WR_RS <= add_WR_GC;
-      if((srst_r == 1'b 1)) begin
+      if((srst_r == 1'b1)) begin
         add_RD <= {5{1'b0}};
         add_RD_GC <= {5{1'b0}};
-        add_RD_GCwc <= 5'b 11000;
+        add_RD_GCwc <= 5'b11000;
       end
-      else if((add_RD_CE == 1'b 1)) begin
+      else if((add_RD_CE == 1'b1)) begin
         add_RD <= n_add_RD;
         add_RD_GC[0] <= n_add_RD[0] ^ n_add_RD[1];
         add_RD_GC[1] <= n_add_RD[1] ^ n_add_RD[2];
@@ -185,38 +185,38 @@ reg isrst_r;
   end
 
   assign empty = iempty;
-  assign iempty = (add_WR_RS == add_RD_GC) ? 1'b 1 : 1'b 0;
+  assign iempty = (add_WR_RS == add_RD_GC) ? 1'b1 : 1'b0;
   //--------------------------------
   //-	sync rest stuff --------------
   //- srst is sync with clk_WR -----
   //- srst_r is sync with clk_RD ---
   //--------------------------------
   always @(posedge clk_WR or posedge rst) begin
-    if((rst == 1'b 1)) begin
-      srst_w <= 1'b 0;
-      isrst_r <= 1'b 0;
+    if((rst == 1'b1)) begin
+      srst_w <= 1'b0;
+      isrst_r <= 1'b0;
     end else begin
       isrst_r <= srst_r;
-      if((srst == 1'b 1)) begin
-        srst_w <= 1'b 1;
+      if((srst == 1'b1)) begin
+        srst_w <= 1'b1;
       end
-      else if((isrst_r == 1'b 1)) begin
-        srst_w <= 1'b 0;
+      else if((isrst_r == 1'b1)) begin
+        srst_w <= 1'b0;
       end
     end
   end
 
   always @(posedge clk_RD or posedge rst) begin
-    if((rst == 1'b 1)) begin
-      srst_r <= 1'b 0;
-      isrst_w <= 1'b 0;
+    if((rst == 1'b1)) begin
+      srst_r <= 1'b0;
+      isrst_w <= 1'b0;
     end else begin
       isrst_w <= srst_w;
-      if((isrst_w == 1'b 1)) begin
-        srst_r <= 1'b 1;
+      if((isrst_w == 1'b1)) begin
+        srst_r <= 1'b1;
       end
       else begin
-        srst_r <= 1'b 0;
+        srst_r <= 1'b0;
       end
     end
   end
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index abfd6bf..feddd03 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -39,9 +39,9 @@ reg status;
 reg [31:0] c[3:0];
 
   always @(posedge clk) begin
-    if({b[1],a[3:2]} == 3'b 001) begin
-      status <= 1'b 1;
-      c[0] <= 16'h FFFF;
+    if({b[1],a[3:2]} == 3'b001) begin
+      status <= 1'b1;
+      c[0] <= 16'hFFFF;
     end
   end
 
diff --git a/translated_examples/test.v b/translated_examples/test.v
index 7e51bc0..e7ce5a2 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -114,9 +114,9 @@ parameter [1:0]
   yellow = 3;
 
 reg [1:0] status;
-parameter PARAM1 = 8'b 01101101;
-parameter PARAM2 = 8'b 11001101;
-parameter PARAM3 = 8'b 00010111;
+parameter PARAM1 = 8'b01101101;
+parameter PARAM2 = 8'b11001101;
+parameter PARAM3 = 8'b00010111;
 wire [7:0] param;
 reg selection;
 reg start; wire enf;  // Start and enable signals
@@ -125,47 +125,47 @@ wire [5:0] memaddr;
 wire [13:0] memdout;
 reg [1:0] colour;
 
-  assign param = config == 1'b 1 ? PARAM1 : status == green ? PARAM2 : PARAM3;
+  assign param = config == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3;
   // Synchronously process
   always @(posedge clk) begin
-    pixel_out <= pixel_in ^ 8'b 11001100;
+    pixel_out <= pixel_in ^ 8'b11001100;
   end
 
   // Synchronous process
   always @(posedge clk) begin
     case(status)
     red : begin
-      colour <= 2'b 00;
+      colour <= 2'b00;
     end
     green : begin
-      colour <= 2'b 01;
+      colour <= 2'b01;
     end
     blue : begin
-      colour <= 2'b 10;
+      colour <= 2'b10;
     end
     default : begin
-      colour <= 2'b 11;
+      colour <= 2'b11;
     end
     endcase
   end
 
   // Synchronous process with asynch reset
   always @(posedge clk or posedge rstn) begin
-    if(rstn == 1'b 0) begin
+    if(rstn == 1'b0) begin
       status <= red;
     end else begin
       case(status)
       red : begin
-        if(pix_req == 1'b 1) begin
+        if(pix_req == 1'b1) begin
           status <= green;
         end
       end
       green : begin
-        if(a[3] == 1'b 1) begin
+        if(a[3] == 1'b1) begin
           start <= start_dec;
           status <= blue;
         end
-        else if(({b[5],a[3:2]}) == 3'b 001) begin
+        else if(({b[5],a[3:2]}) == 3'b001) begin
           status <= yellow;
         end
       end
@@ -173,7 +173,7 @@ reg [1:0] colour;
         status <= yellow;
       end
       default : begin
-        start <= 1'b 0;
+        start <= 1'b0;
         status <= red;
       end
       endcase
@@ -183,30 +183,30 @@ reg [1:0] colour;
   // Example of with statement
   always @(*) begin
     case(memaddr[2:0])
-      3'b 000,3'b 110 : code[9:2] <= {3'b 110,pack[6:2]};
-      3'b 101 : code[9:2] <= 8'b 11100010;
-      3'b 010 : code[9:2] <= {8{1'b1}};
-      3'b 011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b + 1'b 1;
+      3'b000,3'b110 : code[9:2] <= {3'b110,pack[6:2]};
+      3'b101 : code[9:2] <= 8'b11100010;
+      3'b010 : code[9:2] <= {8{1'b1}};
+      3'b011 : code[9:2] <= {8{1'b0}};
+      default : code[9:2] <= a + b + 1'b1;
     endcase
   end
 
   assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
   // Asynch process
   always @(we or addr or config or bip) begin
-    if(we == 1'b 1) begin
-      if(addr[2:0] == 3'b 100) begin
-        selection <= 1'b 1;
+    if(we == 1'b1) begin
+      if(addr[2:0] == 3'b100) begin
+        selection <= 1'b1;
       end
-      else if(({b,a}) == {a,b} && bip == 1'b 0) begin
+      else if(({b,a}) == {a,b} && bip == 1'b0) begin
         selection <= config;
       end
       else begin
-        selection <= 1'b 1;
+        selection <= 1'b1;
       end
     end
     else begin
-      selection <= 1'b 0;
+      selection <= 1'b0;
     end
   end
 
@@ -238,8 +238,8 @@ reg [1:0] colour;
     // Outputs
     .dout(memdin));
 
-  assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001};
-  assign enf = a == (7'b 1101111 + load) && c < 7'b 1000111 ? 1'b 1 : 1'b 0;
+  assign complex = {enf,(3'b110 * load),qtd[3:0],base,5'b11001};
+  assign enf = a == (7'b1101111 + load) && c < 7'b1000111 ? 1'b1 : 1'b0;
   assign eno = enf;
 
 endmodule