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authorLarry Doolittle <ldoolitt@recycle.lbl.gov>2017-11-28 20:28:24 -0800
committerLarry Doolittle <ldoolitt@recycle.lbl.gov>2017-11-28 20:28:24 -0800
commit051a68e5336ee1f575518be08e5c3e6b2b549c42 (patch)
treee714fee06958a23d313d8168eaeb1153835827a4
parent28e612f9b63fce6ea7fe933ddfcd39e7f132cd4c (diff)
downloadvhdl2vl-051a68e5336ee1f575518be08e5c3e6b2b549c42.zip
vhdl2vl-051a68e5336ee1f575518be08e5c3e6b2b549c42.tar.gz
Add testcase for underscore in NATURAL
-rw-r--r--examples/based.vhd3
-rw-r--r--translated_examples/based.v3
2 files changed, 4 insertions, 2 deletions
diff --git a/examples/based.vhd b/examples/based.vhd
index 1a8d2a1..7020b83 100644
--- a/examples/based.vhd
+++ b/examples/based.vhd
@@ -4,9 +4,10 @@ USE IEEE.std_logic_1164.all;
entity based is port( sysclk : in std_logic);
end based;
architecture rtl of based is
- signal foo,foo2,foo8,foo10,foo11,foo16 : integer;
+ signal foo,foo1,foo2,foo8,foo10,foo11,foo16 : integer;
begin
foo <= 123;
+ foo1 <= 123_456;
foo2 <= 2#00101101110111#;
foo8 <= 8#0177362#;
foo10<= 10#01234#;
diff --git a/translated_examples/based.v b/translated_examples/based.v
index e1386c8..45336dc 100644
--- a/translated_examples/based.v
+++ b/translated_examples/based.v
@@ -7,9 +7,10 @@ input wire sysclk
-wire [31:0] foo; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16;
+wire [31:0] foo; wire [31:0] foo1; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16;
assign foo = 123;
+ assign foo1 = 123456;
assign foo2 = 'B00101101110111;
assign foo8 = 'O0177362;
assign foo10 = 'D01234;
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