Added scientific notation supports for integers and floats

Also support was added for real numbers especially thinking in generics.
Files called scientific.vhd and scientific.v were added for test.

5 files changed, 71 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index e01e53d..dadb49d 100644
--- a/Makefile
+++ b/Makefile
@@ -6,7 +6,10 @@ VHDLS    = $(notdir $(EXAMPLES))
 
 all: diff
 
-translate:
+src/vhd2vl:
+	make -C src
+
+translate: src/vhd2vl
 	@mkdir -p temp/verilog
 	@$(foreach VHDL,$(VHDLS),cd examples; ../src/vhd2vl $(VHDL) ../temp/verilog/$(basename $(VHDL)).v)
 
diff --git a/examples/scientific.vhd b/examples/scientific.vhd
new file mode 100644
index 0000000..d71e55d
--- /dev/null
+++ b/examples/scientific.vhd
@@ -0,0 +1,13 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity Scientific is
+   generic (
+      exp1: integer := 25e6;
+      exp2: integer := 25E6;
+      exp3: real    := 25.0e6
+   );
+   port(
+      clk : in std_logic
+   );
+end Scientific;
diff --git a/src/vhd2vl.l b/src/vhd2vl.l
index 661824f..e7419de 100644
--- a/src/vhd2vl.l
+++ b/src/vhd2vl.l
@@ -84,6 +84,7 @@ void getbasedstring(unsigned skip);
 "unsigned" |
 "std_logic_vector" |
 "std_ulogic_vector" { return BITVECT; }
+"real" { return REAL; }
 "downto" { return DOWNTO; }
 "to" { return TO; }
 "type" {return TYPE; }
@@ -148,6 +149,13 @@ void getbasedstring(unsigned skip);
   return NATURAL;
 }
 
+[0-9]+e[0-9]+ |
+[0-9]+\.[0-9]+e[0-9]+ {
+  yylval.txt=malloc(strlen(yytext)+1);
+  strcpy(yylval.txt, yytext);
+  return SCIENTIFIC;
+}
+
 [0-9]+\.[0-9]+ {
   getstring(0);
   return FLOAT;
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index 9847f4a..9525785 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -703,6 +703,7 @@ slist *emit_io_list(slist *sl)
 %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
 %token <txt> STRING NAME RANGE NULLV OPEN
 %token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT LEFT
+%token <txt> SCIENTIFIC REAL
 %token <n> NATURAL
 
 %type <n> trad
@@ -1033,6 +1034,9 @@ type        : BIT {
                 $$->nlo = addtxt(NULL,"0");
                 $$->nhi = addtxt(NULL,"31");
               }
+            | REAL {
+                $$=new_vrange(tSCALAR);
+              }
             | BITVECT '(' vec_range ')' {$$=$3;}
             | NAME {
               sglist *sg;
@@ -2054,6 +2058,12 @@ expr : signal {
            e->sl=addvec(NULL,$1);
            $$=e;
          }
+     | SCIENTIFIC {
+         expdata *e=xmalloc(sizeof(expdata));
+           e->op='t'; /* Terminal symbol */
+           e->sl=addtxt(NULL,$1);
+           $$=e;
+         }
      | FLOAT {
          expdata *e=xmalloc(sizeof(expdata));
            e->op='t'; /* Terminal symbol */
diff --git a/translated_examples/scientific.v b/translated_examples/scientific.v
new file mode 100644
index 0000000..e5b301b
--- /dev/null
+++ b/translated_examples/scientific.v
@@ -0,0 +1,36 @@
+// File scientific.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 1995
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+
+module Scientific(
+clk
+);
+
+parameter [31:0] exp1=25e6;
+parameter [31:0] exp2=25E6;
+parameter exp3=25.0e6;
+input clk;
+
+wire clk;
+
+
+
+endmodule