diff options
| -rw-r--r-- | examples/based.vhd | 3 | ||||
| -rw-r--r-- | translated_examples/based.v | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/examples/based.vhd b/examples/based.vhd index 1a8d2a1..7020b83 100644 --- a/examples/based.vhd +++ b/examples/based.vhd @@ -4,9 +4,10 @@ USE IEEE.std_logic_1164.all; entity based is port( sysclk : in std_logic); end based; architecture rtl of based is - signal foo,foo2,foo8,foo10,foo11,foo16 : integer; + signal foo,foo1,foo2,foo8,foo10,foo11,foo16 : integer; begin foo <= 123; + foo1 <= 123_456; foo2 <= 2#00101101110111#; foo8 <= 8#0177362#; foo10<= 10#01234#; diff --git a/translated_examples/based.v b/translated_examples/based.v index e1386c8..45336dc 100644 --- a/translated_examples/based.v +++ b/translated_examples/based.v @@ -7,9 +7,10 @@ input wire sysclk -wire [31:0] foo; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16; +wire [31:0] foo; wire [31:0] foo1; wire [31:0] foo2; wire [31:0] foo8; wire [31:0] foo10; wire [31:0] foo11; wire [31:0] foo16; assign foo = 123; + assign foo1 = 123456; assign foo2 = 'B00101101110111; assign foo8 = 'O0177362; assign foo10 = 'D01234; |
