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author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-19 13:07:50 -0300 |
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committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-19 13:07:50 -0300 |
commit | 9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8 (patch) | |
tree | 0055d2f9e9a2a2f12c5a107e8a2599e60d308d68 | |
parent | 1ac8bf5886ade040002ff53e4d460fe4010140eb (diff) | |
download | vhdl2vl-9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8.tar.gz vhdl2vl-9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8.zip |
Fixes in examples and translated examples to avoid some complains of iVerilog
'test' was repeated as entity/module name
'config' was used as port name and is a reserved word in Verilog.
-rw-r--r-- | examples/generic.vhd | 6 | ||||
-rw-r--r-- | examples/genericmap.vhd | 8 | ||||
-rw-r--r-- | examples/ifchain.vhd | 6 | ||||
-rw-r--r-- | examples/test.vhd | 8 | ||||
-rw-r--r-- | translated_examples/generic.v | 2 | ||||
-rw-r--r-- | translated_examples/genericmap.v | 3 | ||||
-rw-r--r-- | translated_examples/ifchain.v | 2 | ||||
-rw-r--r-- | translated_examples/test.v | 8 |
8 files changed, 21 insertions, 22 deletions
diff --git a/examples/generic.vhd b/examples/generic.vhd index e3b6801..8a12b50 100644 --- a/examples/generic.vhd +++ b/examples/generic.vhd @@ -1,7 +1,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; -entity test is +entity generic1 is generic( dog_width : std_logic_vector(7 downto 0) := "10101100"; bus_width : integer := 32 @@ -9,8 +9,8 @@ entity test is port( reset, sysclk : in std_logic; a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) ); -end test; -architecture rtl of test is +end generic1; +architecture rtl of generic1 is signal foo : std_logic_vector(1+1 downto 0); signal code,code1: std_logic_vector(9 downto 0); signal egg : std_logic_vector(324 to 401); diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd index 1132554..33d9363 100644 --- a/examples/genericmap.vhd +++ b/examples/genericmap.vhd @@ -1,6 +1,6 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all; -entity test is +entity genericmap is generic( rst_val : std_logic := '0'; thing_size: integer := 201; @@ -13,7 +13,7 @@ port( we : in std_logic; pixel_in : in std_logic_vector(7 downto 0); pix_req : in std_logic; - config, bip : in std_logic; + bip : in std_logic; a, b : in std_logic_vector(7 downto 0); c, load : in std_logic_vector(7 downto 0); pack : in std_logic_vector(6 downto 0); @@ -27,8 +27,8 @@ port( complex : out std_logic_vector(23 downto 0); eno : out std_logic ); -end test; -architecture rtl of test is +end genericmap; +architecture rtl of genericmap is component dsp generic( diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd index dbc0a98..a830272 100644 --- a/examples/ifchain.vhd +++ b/examples/ifchain.vhd @@ -1,12 +1,12 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all; -entity test is port( +entity ifchain is port( clk, rstn : in std_logic ); -end test; +end ifchain; -architecture rtl of test is +architecture rtl of ifchain is type t is array (3 downto 0) of std_logic_vector(31 downto 0); signal a : std_logic_vector(3 downto 0); signal b : std_logic_vector(3 downto 0); diff --git a/examples/test.vhd b/examples/test.vhd index bcc2968..b273e8f 100644 --- a/examples/test.vhd +++ b/examples/test.vhd @@ -18,7 +18,7 @@ entity test is port( we : in std_logic; pixel_in : in std_logic_vector(7 downto 0); pix_req : in std_logic; - config, bip : in std_logic; + config1, bip : in std_logic; a, b : in std_logic_vector(7 downto 0); c, load : in std_logic_vector(7 downto 0); pack : in std_logic_vector(6 downto 0); @@ -82,7 +82,7 @@ end component; signal colour : std_logic_vector(1 downto 0); begin - param <= PARAM1 when config = '1' else PARAM2 when status = green else PARAM3; + param <= PARAM1 when config1 = '1' else PARAM2 when status = green else PARAM3; -- Synchronously process process(clk) begin @@ -139,12 +139,12 @@ begin code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); -- Asynch process - decode : process(we, addr, config, bip) begin + decode : process(we, addr, config1, bip) begin if we = '1' then if addr(2 downto 0) = "100" then selection <= '1'; elsif (b & a) = a & b and bip = '0' then - selection <= config; + selection <= config1; else selection <= '1'; end if; diff --git a/translated_examples/generic.v b/translated_examples/generic.v index c436e64..c195ad2 100644 --- a/translated_examples/generic.v +++ b/translated_examples/generic.v @@ -1,6 +1,6 @@ // no timescale needed -module test( +module generic1( input wire reset, input wire sysclk, input wire [bus_width:0] a, diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v index e09865f..578f491 100644 --- a/translated_examples/genericmap.v +++ b/translated_examples/genericmap.v @@ -1,6 +1,6 @@ // no timescale needed -module test( +module genericmap( input wire clk, input wire rstn, input wire en, @@ -10,7 +10,6 @@ input wire [25:0] din, input wire we, input wire [7:0] pixel_in, input wire pix_req, -input wire config, input wire bip, input wire [7:0] a, input wire [7:0] b, diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v index ad22a8d..e037889 100644 --- a/translated_examples/ifchain.v +++ b/translated_examples/ifchain.v @@ -1,6 +1,6 @@ // no timescale needed -module test( +module ifchain( input wire clk, input wire rstn ); diff --git a/translated_examples/test.v b/translated_examples/test.v index aa3fe85..97e79ac 100644 --- a/translated_examples/test.v +++ b/translated_examples/test.v @@ -16,7 +16,7 @@ input wire [25:0] din, input wire we, input wire [7:0] pixel_in, input wire pix_req, -input wire config, +input wire config1, input wire bip, input wire [7:0] a, input wire [7:0] b, @@ -59,7 +59,7 @@ wire [5:0] memaddr; wire [13:0] memdout; reg [1:0] colour; - assign param = config == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3; + assign param = config1 == 1'b1 ? PARAM1 : status == green ? PARAM2 : PARAM3; // Synchronously process always @(posedge clk) begin pixel_out <= pixel_in ^ 8'b11001100; @@ -127,13 +127,13 @@ reg [1:0] colour; assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); // Asynch process - always @(we, addr, config, bip) begin + always @(we, addr, config1, bip) begin if(we == 1'b1) begin if(addr[2:0] == 3'b100) begin selection <= 1'b1; end else if(({b,a}) == {a,b} && bip == 1'b0) begin - selection <= config; + selection <= config1; end else begin selection <= 1'b1; |