Examples were corrected according to GHDL complains

5 files changed, 10 insertions, 8 deletions

diff --git a/examples/dsp.vhd b/examples/dsp.vhd
index 7dedb47..cf0bfc7 100644
--- a/examples/dsp.vhd
+++ b/examples/dsp.vhd
@@ -1,6 +1,7 @@
 -- Nearly useless stub, it's here to support genericmap.vhd
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
 
 entity dsp is generic(
   rst_val   : std_logic := '0';
@@ -27,6 +28,6 @@ architecture rtl of dsp is
     signal foo : std_logic;
 begin
     process(clk) begin
-       dout <= '1';
+       dout <= std_logic_vector(to_unsigned(1,bus_width));
     end process;
 end rtl;
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 9da3806..9d0760d 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -68,7 +68,7 @@ begin
     start => '0',
     param => X"42",
     addr => "101",
-    din => X"111111",
+    din => "00" & X"111111",
     we => '0',
     -- Outputs
     dout => dout(23 downto 0),
@@ -88,7 +88,7 @@ begin
     start => '0',
     param => X"42",
     addr => "101",
-    din => X"1111",
+    din => "00" & X"001111",
     we => '0',
     -- Outputs
     dout => dout(15 downto 0),
diff --git a/examples/ifchain2.vhd b/examples/ifchain2.vhd
index e179960..6b12150 100644
--- a/examples/ifchain2.vhd
+++ b/examples/ifchain2.vhd
@@ -1,5 +1,6 @@
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
 
 entity ifchain is port(
   clk, rstn : in std_logic;
@@ -9,8 +10,8 @@ entity ifchain is port(
 end ifchain;
 
 architecture rtl of ifchain is
-  signal counter : std_logic_vector(3 downto 0);
-  constant CLK_DIV_VAL : unsigned(3 downto 0) := 11;
+  signal counter : unsigned(3 downto 0);
+  constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4);
 begin
 
 clk_src : process(clk, rstn) is
diff --git a/examples/mem.vhd b/examples/mem.vhd
index 7b96b65..408051f 100644
--- a/examples/mem.vhd
+++ b/examples/mem.vhd
@@ -23,13 +23,13 @@ architecture rtl of mem is
   signal mem : mem_Type;
   signal al : unsigned(addr_width-1 downto 0) := X"00";
 begin
-  dout <= mem(al);
+  dout <= mem(to_integer(al));
   process (clk) is
   begin
     if rising_edge(clk) then
       al <= addr;
       if en = '1' then
-        mem(addr) <= din;
+        mem(to_integer(addr)) <= din;
       end if;
     end if;
   end process;
diff --git a/examples/signextend.vhd b/examples/signextend.vhd
index 2f8d9ee..48b7130 100644
--- a/examples/signextend.vhd
+++ b/examples/signextend.vhd
@@ -1,6 +1,6 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
 
 entity signextend is
     port(