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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* Remember if LR register has been spilled in this function.Evan Cheng2007-01-291-1/+5
| | | | llvm-svn: 33632
* Represent tADDspi and tSUBspi as two-address instructions.Evan Cheng2007-01-261-1/+1
| | | | llvm-svn: 33551
* I am an idiot.Evan Cheng2007-01-251-1/+1
| | | | llvm-svn: 33509
* PEI is now responsible for adding MaxCallFrameSize to frame size and align ↵Evan Cheng2007-01-231-15/+0
| | | | | | the stack. Each target can further adjust the frame size if necessary. llvm-svn: 33460
* hasFP() is now a virtual method of MRegisterInfo.Evan Cheng2007-01-231-1/+1
| | | | llvm-svn: 33455
* Round up stack to multiple of alignment only if it's a leaf function without ↵Evan Cheng2007-01-201-4/+7
| | | | | | alloca. llvm-svn: 33401
* Prologue and epilogue bugs for non-Darwin targets.Evan Cheng2007-01-201-22/+46
| | | | llvm-svn: 33390
* Clean up ARM PEI code.Evan Cheng2007-01-201-79/+65
| | | | llvm-svn: 33389
* isDarwin -> isTargetDarwinEvan Cheng2007-01-191-3/+3
| | | | llvm-svn: 33366
* ARM backend contribution from Apple.Evan Cheng2007-01-191-124/+904
| | | | llvm-svn: 33353
* Don't add or sub zero to sp.Lauro Ramos Venancio2007-01-121-6/+10
| | | | llvm-svn: 33142
* Build constants using instructions mov/orr or mvn/eor.Lauro Ramos Venancio2007-01-121-69/+6
| | | | llvm-svn: 33141
* Fix naming inconsistency.Evan Cheng2007-01-021-6/+6
| | | | llvm-svn: 32823
* macros -> Inline functionsRafael Espindola2006-12-181-9/+13
| | | | | | Lauros's patch llvm-svn: 32656
* Avoid creating invalid sub/add instructions on the prolog/epilogRafael Espindola2006-12-141-10/+86
| | | | | | patch by Lauro llvm-svn: 32577
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | llvm-svn: 32333
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-16/+18
| | | | | | of opcode and number of operands. llvm-svn: 31947
* implement load effective address similar to the alpha backendRafael Espindola2006-11-091-4/+4
| | | | | | remove lea_addri and the now unused memri addressing mode llvm-svn: 31592
* initial implementation of addressing mode 2Rafael Espindola2006-11-081-9/+9
| | | | | | TODO: fix lea_addri llvm-svn: 31552
* add support for calling functions when the caller has variable sized objectsRafael Espindola2006-10-311-1/+19
| | | | llvm-svn: 31312
* initial support for frame pointersRafael Espindola2006-10-261-4/+37
| | | | llvm-svn: 31197
* add the immediate to the Offset in eliminateFrameIndexRafael Espindola2006-10-171-2/+2
| | | | llvm-svn: 30998
* add FCPYS and FCPYDRafael Espindola2006-10-171-3/+11
| | | | llvm-svn: 30995
* fix the stack alignmentRafael Espindola2006-10-061-0/+3
| | | | llvm-svn: 30766
* add shifts to addressing mode 1Rafael Espindola2006-09-131-4/+8
| | | | llvm-svn: 30291
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-111-4/+4
| | | | llvm-svn: 30252
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-2/+2
| | | | | | def operand or a use operand. llvm-svn: 30109
* add a "load effective address"Rafael Espindola2006-08-171-1/+2
| | | | llvm-svn: 29748
* Declare the callee saved regsRafael Espindola2006-08-161-8/+10
| | | | | | | Remove the hard coded store and load of the link register Implement ARMFrameInfo llvm-svn: 29727
* correctly set LocalAreaOffset of TargetFrameInfoRafael Espindola2006-08-091-5/+0
| | | | llvm-svn: 29589
* fix the spill codeRafael Espindola2006-08-091-7/+9
| | | | llvm-svn: 29583
* fix the loading of the link register in emitepilogueRafael Espindola2006-08-091-1/+3
| | | | llvm-svn: 29580
* change the addressing mode of the str instruction to reg+immRafael Espindola2006-08-081-4/+2
| | | | llvm-svn: 29571
* initial support for variable number of argumentsRafael Espindola2006-08-081-8/+17
| | | | llvm-svn: 29567
* implemented subRafael Espindola2006-07-211-3/+8
| | | | | | correctly update the stack pointer in the prologue and epilogue llvm-svn: 29244
* initial prologue and epilogue implementation. Need to define add and sub ↵Rafael Espindola2006-07-181-0/+20
| | | | | | before finishing it :-) llvm-svn: 29175
* add the memri memory operandRafael Espindola2006-07-111-8/+18
| | | | | | this makes it possible for ldr instructions with non-zero immediate llvm-svn: 29103
* create the raddr addressing mode that matches any register and the frame indexRafael Espindola2006-07-101-1/+1
| | | | | | | | | use raddr for the ldr instruction. This removes a dummy mov from the assembly output remove SelectFrameIndex remove isLoadFromStackSlot remove isStoreToStackSlot llvm-svn: 29079
* handle the "mov reg1, reg2" case in isMoveInstrRafael Espindola2006-06-271-1/+1
| | | | llvm-svn: 28945
* initial implementation of ARMRegisterInfo::eliminateFrameIndexRafael Espindola2006-06-181-1/+23
| | | | | | fixes test/Regression/CodeGen/ARM/ret_arg5.ll llvm-svn: 28854
* implement movriRafael Espindola2006-05-181-1/+1
| | | | | | add a stub LowerFORMAL_ARGUMENTS llvm-svn: 28388
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+11
| | | | llvm-svn: 28378
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+91
llvm-svn: 28301
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