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authorEvan Cheng <evan.cheng@apple.com>2007-01-26 21:33:19 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-01-26 21:33:19 +0000
commitadd7f164a1d78dfc4722accebaea4bcefdf57246 (patch)
tree37efb35788415e27bf9608f226eaa35e5d5e6263 /llvm/lib/Target/ARM/ARMRegisterInfo.cpp
parentc56315c2b538fb5f95178254fe8a4f10578487c4 (diff)
downloadbcm5719-llvm-add7f164a1d78dfc4722accebaea4bcefdf57246.tar.gz
bcm5719-llvm-add7f164a1d78dfc4722accebaea4bcefdf57246.zip
Represent tADDspi and tSUBspi as two-address instructions.
llvm-svn: 33551
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 68eb616d7fe..912d17adc13 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -378,7 +378,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
Bytes -= ThisVal;
// Build the new tADD / tSUB.
if (isTwoAddr)
- BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal);
+ BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
else {
BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
BaseReg = DestReg;
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