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authorRafael Espindola <rafael.espindola@gmail.com>2006-08-17 17:09:40 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-08-17 17:09:40 +0000
commitc3ed77e1b91354a0e54936f2a095d6186bff7133 (patch)
tree5b8b95e01a03644f9a31785005b0e3182960a412 /llvm/lib/Target/ARM/ARMRegisterInfo.cpp
parent1c3210d08dbb73cf94e9db45c2b8de56208bc63e (diff)
downloadbcm5719-llvm-c3ed77e1b91354a0e54936f2a095d6186bff7133.tar.gz
bcm5719-llvm-c3ed77e1b91354a0e54936f2a095d6186bff7133.zip
add a "load effective address"
llvm-svn: 29748
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index a9c30c40c7e..c5eef119520 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -89,7 +89,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::ldr ||
- MI.getOpcode() == ARM::str);
+ MI.getOpcode() == ARM::str ||
+ MI.getOpcode() == ARM::lea_addri);
unsigned FrameIdx = 2;
unsigned OffIdx = 1;
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