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authorRafael Espindola <rafael.espindola@gmail.com>2006-11-09 13:58:55 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-11-09 13:58:55 +0000
commit5f7ab1b964a465f4f9e19d6c80a186515cdcb2e5 (patch)
treeef4dc501f4d21895de330be1f55a3c10783557da /llvm/lib/Target/ARM/ARMRegisterInfo.cpp
parent48b21d50243714295645db43a9e15d6947cede73 (diff)
downloadbcm5719-llvm-5f7ab1b964a465f4f9e19d6c80a186515cdcb2e5.tar.gz
bcm5719-llvm-5f7ab1b964a465f4f9e19d6c80a186515cdcb2e5.zip
implement load effective address similar to the alpha backend
remove lea_addri and the now unused memri addressing mode llvm-svn: 31592
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 4a8fa1ee4d1..3b5ed6a0fad 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -129,11 +129,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::LDR ||
- MI.getOpcode() == ARM::STR ||
- MI.getOpcode() == ARM::lea_addri);
+ MI.getOpcode() == ARM::STR ||
+ MI.getOpcode() == ARM::ADD);
- unsigned FrameIdx = MI.getOpcode() == ARM::lea_addri ? 2 : 1;
- unsigned OffIdx = MI.getOpcode() == ARM::lea_addri ? 1 : 2;
+ unsigned FrameIdx = 1;
+ unsigned OffIdx = 2;
int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
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