added a skeleton of the ARM backend

llvm-svn: 28301

1 files changed, 91 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
new file mode 100644
index 00000000000..db5ce68f4be
--- /dev/null
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -0,0 +1,91 @@
+//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the "Instituto Nokia de Tecnologia" and
+// is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the ARM implementation of the MRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARM.h"
+#include "ARMRegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/Type.h"
+#include "llvm/ADT/STLExtras.h"
+#include <iostream>
+using namespace llvm;
+
+ARMRegisterInfo::ARMRegisterInfo()
+  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
+}
+
+void ARMRegisterInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                    unsigned SrcReg, int FI,
+                    const TargetRegisterClass *RC) const {
+  // On the order of operands here: think "[FI + 0] = SrcReg".
+  assert (RC == ARM::IntRegsRegisterClass);
+  BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+}
+
+void ARMRegisterInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                     unsigned DestReg, int FI,
+                     const TargetRegisterClass *RC) const {
+  assert (RC == ARM::IntRegsRegisterClass);
+  BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
+}
+
+void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+                                     MachineBasicBlock::iterator I,
+                                     unsigned DestReg, unsigned SrcReg,
+                                     const TargetRegisterClass *RC) const {
+  assert (RC == ARM::IntRegsRegisterClass);
+  BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
+}
+
+MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
+                                                   unsigned OpNum,
+                                                   int FI) const {
+  return NULL;
+}
+
+void ARMRegisterInfo::
+eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator I) const {
+  MBB.erase(I);
+}
+
+void
+ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+  assert(0 && "Not Implemented");
+}
+
+void ARMRegisterInfo::
+processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
+
+void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
+}
+
+void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
+				   MachineBasicBlock &MBB) const {
+}
+
+unsigned ARMRegisterInfo::getRARegister() const {
+  return ARM::R14;
+}
+
+unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return ARM::R13;
+}
+
+#include "ARMGenRegisterInfo.inc"
+