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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* Remember if LR register has been spilled in this function.Evan Cheng2007-01-291-1/+5
* Represent tADDspi and tSUBspi as two-address instructions.Evan Cheng2007-01-261-1/+1
* I am an idiot.Evan Cheng2007-01-251-1/+1
* PEI is now responsible for adding MaxCallFrameSize to frame size and align th...Evan Cheng2007-01-231-15/+0
* hasFP() is now a virtual method of MRegisterInfo.Evan Cheng2007-01-231-1/+1
* Round up stack to multiple of alignment only if it's a leaf function without ...Evan Cheng2007-01-201-4/+7
* Prologue and epilogue bugs for non-Darwin targets.Evan Cheng2007-01-201-22/+46
* Clean up ARM PEI code.Evan Cheng2007-01-201-79/+65
* isDarwin -> isTargetDarwinEvan Cheng2007-01-191-3/+3
* ARM backend contribution from Apple.Evan Cheng2007-01-191-124/+904
* Don't add or sub zero to sp.Lauro Ramos Venancio2007-01-121-6/+10
* Build constants using instructions mov/orr or mvn/eor.Lauro Ramos Venancio2007-01-121-69/+6
* Fix naming inconsistency.Evan Cheng2007-01-021-6/+6
* macros -> Inline functionsRafael Espindola2006-12-181-9/+13
* Avoid creating invalid sub/add instructions on the prolog/epilogRafael Espindola2006-12-141-10/+86
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-16/+18
* implement load effective address similar to the alpha backendRafael Espindola2006-11-091-4/+4
* initial implementation of addressing mode 2Rafael Espindola2006-11-081-9/+9
* add support for calling functions when the caller has variable sized objectsRafael Espindola2006-10-311-1/+19
* initial support for frame pointersRafael Espindola2006-10-261-4/+37
* add the immediate to the Offset in eliminateFrameIndexRafael Espindola2006-10-171-2/+2
* add FCPYS and FCPYDRafael Espindola2006-10-171-3/+11
* fix the stack alignmentRafael Espindola2006-10-061-0/+3
* add shifts to addressing mode 1Rafael Espindola2006-09-131-4/+8
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-111-4/+4
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-2/+2
* add a "load effective address"Rafael Espindola2006-08-171-1/+2
* Declare the callee saved regsRafael Espindola2006-08-161-8/+10
* correctly set LocalAreaOffset of TargetFrameInfoRafael Espindola2006-08-091-5/+0
* fix the spill codeRafael Espindola2006-08-091-7/+9
* fix the loading of the link register in emitepilogueRafael Espindola2006-08-091-1/+3
* change the addressing mode of the str instruction to reg+immRafael Espindola2006-08-081-4/+2
* initial support for variable number of argumentsRafael Espindola2006-08-081-8/+17
* implemented subRafael Espindola2006-07-211-3/+8
* initial prologue and epilogue implementation. Need to define add and sub befo...Rafael Espindola2006-07-181-0/+20
* add the memri memory operandRafael Espindola2006-07-111-8/+18
* create the raddr addressing mode that matches any register and the frame indexRafael Espindola2006-07-101-1/+1
* handle the "mov reg1, reg2" case in isMoveInstrRafael Espindola2006-06-271-1/+1
* initial implementation of ARMRegisterInfo::eliminateFrameIndexRafael Espindola2006-06-181-1/+23
* implement movriRafael Espindola2006-05-181-1/+1
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+11
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+91
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