Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Fixed partselect example | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -2/+2 |
* | Correct selection of -: vs. +: | Larry Doolittle | 2017-11-25 | 1 | -1/+3 |
* | Add missing CONVFUNC_1 to grammar | Larry Doolittle | 2017-11-24 | 1 | -1/+1 |
* | Fixed dsp.vhd | Rodrigo Alejandro Melo | 2017-11-24 | 1 | -13/+15 |
* | Turn off debug prints and fix warnings | Larry Doolittle | 2017-11-23 | 2 | -2/+7 |
* | First stupid attempt to finish part select | Larry Doolittle | 2017-11-23 | 4 | -5/+12 |
* | Added partselect example | Rodrigo Alejandro Melo | 2017-11-23 | 1 | -0/+30 |
* | Allow second argument to CONVFUNC_2 to be expr | Larry Doolittle | 2017-11-22 | 1 | -1/+1 |
* | Experimental support of exponentiation | Rodrigo Alejandro Melo | 2017-11-21 | 1 | -1/+8 |
* | Adding support for while loop | Larry Doolittle | 2017-11-20 | 1 | -0/+28 |
* | Align the prototypes for dsp in dsp and genericmap | Larry Doolittle | 2017-11-20 | 2 | -4/+3 |
* | Beginning support for assertions | Larry Doolittle | 2017-11-18 | 1 | -0/+1 |
* | Simple fix to genericmap example | Larry Doolittle | 2017-11-18 | 1 | -2/+2 |
* | Modified the Makefile to run GHDl and iVerilog always but only if installed | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -1/+3 |
* | Added (partial) support for to_integer function | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+6 |
* | Changes on genericmap due to unsupported port assignment | Rodrigo Alejandro Melo | 2017-11-16 | 2 | -5/+24 |
* | The resulting files of the GHDL analysis were moved to temp/vhdl | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+5 |
* | Added the special file examples/todo.vhd | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -0/+20 |
* | Examples were corrected according to GHDL complains | Rodrigo Alejandro Melo | 2017-11-16 | 5 | -8/+10 |
* | Squelch some trailing whitespace | Larry Doolittle | 2017-11-12 | 4 | -17/+16 |
* | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 4 | -7/+94 |
* | New make target: verilogcheck | Larry Doolittle | 2017-11-10 | 2 | -0/+23 |
* | New rem before END PROCESS | Larry Doolittle | 2017-11-10 | 1 | -0/+32 |
* | Experiment with OTHERS logic | Larry Doolittle | 2017-11-09 | 1 | -0/+17 |
* | Fixes in examples and translated examples to avoid some complains of iVerilog | Rodrigo Alejandro Melo | 2017-02-19 | 4 | -14/+14 |
* | Promoted unsupported BASED NUMBER from warning to error | Rodrigo Alejandro Melo | 2017-02-19 | 1 | -1/+1 |
* | Added analysis of examples with GHDL | Rodrigo Alejandro Melo | 2017-02-14 | 13 | -33/+37 |
* | Added scientific notation supports for integers and floats | Rodrigo Alejandro Melo | 2017-02-09 | 1 | -0/+13 |
* | vhd2vl-2.4 | Larry Doolittle | 2015-09-20 | 1 | -0/+3 |
* | vhd2vl-2.3 | Larry Doolittle | 2015-09-20 | 1 | -0/+205 |
* | vhd2vl-2.2 | Larry Doolittle | 2015-09-20 | 11 | -0/+1314 |