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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* AMDGPU: Figure out private memory regs after loweringMatt Arsenault2017-07-181-0/+4
* AMDGPU: Partially fix implicit.buffer.ptr intrinsic handlingMatt Arsenault2017-06-261-6/+5
* AMDGPU: Fix scratch wave offset relative FI expansionMatt Arsenault2017-06-191-9/+20
* AMDGPU: Work around build special casing .inc filesMatt Arsenault2017-06-081-1/+2
* AMDGPU: Use correct register names in inline assemblyMatt Arsenault2017-06-081-0/+59
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-8/+35
* AMDGPU: Expand frame indexes to be relative to scratch wave offsetMatt Arsenault2017-05-171-6/+71
* AMDGPU: Use appropriate soffset for spillingMatt Arsenault2017-05-171-13/+13
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-241-0/+3
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-28/+31
* Fix typoMatt Arsenault2017-04-181-1/+1
* [AMDGPU] added SIInstrInfo::getAddNoCarry() helperStanislav Mekhanoshin2017-04-141-3/+1
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-241-16/+0
* Correct register pressure calculation in presence of subregsStanislav Mekhanoshin2017-02-231-0/+16
* AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault2017-02-211-23/+88
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-0/+6
* [AMDGPU] Override PSet for M0Stanislav Mekhanoshin2017-02-101-0/+8
* [AMDGPU] Implement register pressure callbacksStanislav Mekhanoshin2017-02-081-0/+31
* [AMDGPU] Move register related queries to subtarget classKonstantin Zhuravlyov2017-02-081-208/+10
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-4/+6
* [AMDGPU] Do not allow register coalescer to create big superregsStanislav Mekhanoshin2017-01-181-0/+20
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-8/+8
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-1/+2
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-13/+0
* AMDGPU/SI: Don't reserve XNACK when it's disabledMarek Olsak2016-12-091-1/+1
* AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objectsMarek Olsak2016-12-091-6/+15
* AMDGPU/SI: Allow using SGPRs 96-101 on VIMarek Olsak2016-12-091-5/+7
* [AMDGPU] Fix number of reserved SGPRs on CI to reflect flat scratch useStanislav Mekhanoshin2016-12-081-0/+2
* AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameB...Nicolai Haehnle2016-12-081-5/+21
* AMDGPU: remove a couple of unused variablesSaleem Abdulrasool2016-12-031-14/+2
* AMDGPU: Use wider scalar spills for SGPR spillingMatt Arsenault2016-12-021-15/+70
* AMDGPU: Materialize frame index before addMatt Arsenault2016-11-291-1/+6
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-251-75/+200
* Revert "AMDGPU: Implement SGPR spilling with scalar stores"Marek Olsak2016-11-251-99/+7
* Revert "AMDGPU: Fix MMO when splitting spill"Marek Olsak2016-11-251-71/+44
* Revert "AMDGPU: Fix adding extra implicit def of register"Marek Olsak2016-11-251-25/+14
* Revert "AMDGPU: Fix not setting kill flag on temp reg when spilling"Marek Olsak2016-11-251-1/+1
* Revert "AMDGPU: Make m0 unallocatable"Marek Olsak2016-11-251-1/+1
* Revert "AMDGPU: Remove m0 spilling code"Marek Olsak2016-11-251-3/+37
* Revert "AMDGPU: Preserve m0 value when spilling"Marek Olsak2016-11-251-34/+5
* AMDGPU: Preserve m0 value when spillingMatt Arsenault2016-11-241-5/+34
* TRI: Add hook to pass scavenger during frame eliminationMatt Arsenault2016-11-241-0/+10
* AMDGPU: Remove m0 spilling codeMatt Arsenault2016-11-241-37/+3
* AMDGPU: Make m0 unallocatableMatt Arsenault2016-11-241-1/+1
* AMDGPU: Fix not setting kill flag on temp reg when spillingMatt Arsenault2016-11-231-1/+1
* AMDGPU: Fix adding extra implicit def of registerMatt Arsenault2016-11-231-14/+25
* AMDGPU: Fix MMO when splitting spillMatt Arsenault2016-11-231-44/+71
* Fix spelling mistakes in AMDGPU target comments. NFC.Simon Pilgrim2016-11-181-1/+1
* AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies passTom Stellard2016-11-161-11/+14
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