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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
| commit | 9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6 (patch) | |
| tree | b163ccaf77708f0e9a1e3082c207e49e2d8b6d7b /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 8812f28f47a74d32bdd14181ebfe906cbfcd7346 (diff) | |
| download | bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.tar.gz bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.zip | |
AMDGPU: Make m0 unallocatable
m0 may need to be written for spill code, so
we don't want general code uses relying on the
value stored in it.
This introduces a few code quality regressions where copies
from m0 are not coalesced into copies of a copy of m0.
llvm-svn: 287841
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index fb42130767a..37bda5337f4 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -233,7 +233,7 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, MachineRegisterInfo &MRI = MF->getRegInfo(); unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); - unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); + unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) .addImm(Offset); |
