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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* AMDGPU/GlobalISel: Don't use XEXEC class for SGPRsMatt Arsenault2020-01-121-1/+1
* AMDGPU/GlobalISel: Replace handling of boolean valuesMatt Arsenault2020-01-061-8/+0
* Fix broken comment phrasing and indentationMatt Arsenault2019-12-021-7/+6
* AMDGPU: Reuse carry out register during FI eliminationAustin Kerbow2019-11-281-5/+9
* [AMDGPU] Removed dead code handling M0CopyRegStanislav Mekhanoshin2019-11-051-14/+0
* Fix buildbot error in SIRegisterInfo.cpp.Zinovy Nis2019-10-201-3/+4
* AMDGPU: Don't re-get the subtargetMatt Arsenault2019-10-201-21/+9
* [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.Jay Foad2019-10-181-151/+1
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-181-4/+8
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-101-6/+9
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-0/+2
* AMDGPU: Fix an out of date assert in addressing FrameIndexChangpeng Fang2019-10-011-3/+2
* AMDGPU/GlobalISel: Increase max legal size to 1024Matt Arsenault2019-10-011-0/+3
* AMDGPU: Inline constant when materalizing FI with add on gfx9Matt Arsenault2019-09-121-2/+5
* AMDGPU: Make VReg_1 size be 1Matt Arsenault2019-09-091-3/+6
* AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9Matt Arsenault2019-09-041-25/+57
* AMDGPU: Don't use frame virtual registersMatt Arsenault2019-08-291-41/+43
* [AMDGPU] w/a for gfx908 mfma SrcC literal HW bugStanislav Mekhanoshin2019-08-231-0/+10
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-17/+18
* Use MCRegister in MCRegisterInfo's interfacesDaniel Sanders2019-08-021-3/+3
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-3/+3
* [AMDGPU] Reserve all AGPRs on targets which do not have themStanislav Mekhanoshin2019-07-301-0/+8
* [AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin2019-07-191-14/+1
* [AMDGPU] Drop Reg32 and use regular AsmNameStanislav Mekhanoshin2019-07-181-1/+0
* [AMDGPU] Stop special casing flat_scratch for register nameStanislav Mekhanoshin2019-07-171-12/+0
* [AMDGPU] Autogenerate register asm namesStanislav Mekhanoshin2019-07-161-61/+18
* [AMDGPU] gfx908 agpr spillingStanislav Mekhanoshin2019-07-111-17/+108
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-6/+145
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-0/+16
* AMDGPU/GlobalISel: Select G_MERGE_VALUESMatt Arsenault2019-07-091-16/+31
* AMDGPU/GlobalISel: Fix scc->vcc copy handlingMatt Arsenault2019-07-011-2/+2
* AMDGPU: Assert SPAdj is 0Matt Arsenault2019-06-261-0/+2
* AMDGPU/GlobalISel: Select G_TRUNCMatt Arsenault2019-06-241-24/+30
* AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1Matt Arsenault2019-06-241-3/+16
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-4/+4
* AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECTTom Stellard2019-06-171-1/+6
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-1/+28
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-27/+34
* AMDGPU: Disable stack realignment for kernelsMatt Arsenault2019-06-031-0/+13
* [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operandsDmitry Preobrazhensky2019-06-031-0/+5
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-3/+7
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-2/+5
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-011-0/+4
* Reapply "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-271-1/+1
* AMDGPU: Enable the scavenger for large framesMatt Arsenault2019-03-271-5/+14
* Revert "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-251-1/+1
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+32
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-1/+12
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+3
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-3/+6
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