diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-18 20:59:46 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-18 20:59:46 +0000 |
| commit | aa31dce3c5361db38ba613a60a8f776b2b7e2e7a (patch) | |
| tree | 96dd04900d164f70f5a6de9b88762489477a91ca /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 161e2b422316cd57c0285aafb027aa38bd0e4e45 (diff) | |
| download | bcm5719-llvm-aa31dce3c5361db38ba613a60a8f776b2b7e2e7a.tar.gz bcm5719-llvm-aa31dce3c5361db38ba613a60a8f776b2b7e2e7a.zip | |
Fix typo
llvm-svn: 300597
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 36d4df52ff0..098c67252dd 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -124,7 +124,7 @@ unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg( unsigned RegCount = ST.getMaxNumSGPRs(MF); unsigned Reg; - // Try to place it in a hole after PrivateSegmentbufferReg. + // Try to place it in a hole after PrivateSegmentBufferReg. if (RegCount & 3) { // We cannot put the segment buffer in (Idx - 4) ... (Idx - 1) due to // alignment constraints, so we have a hole where can put the wave offset. |
