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| author | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:40 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:40 +0000 |
| commit | 91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3 (patch) | |
| tree | ef2cdaff0b75042f73858032e21b795ade9c06aa /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 1a4ab7e77278f0dcb827451d54a47d6d272f8282 (diff) | |
| download | bcm5719-llvm-91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3.tar.gz bcm5719-llvm-91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3.zip | |
AMDGPU/SI: Allow using SGPRs 96-101 on VI
Summary:
There is no point in setting SGPRS=104, because VI allocates SGPRs
in multiples of 16, so 104 -> 112. That enables us to use all 102 SGPRs
for general purposes.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27149
llvm-svn: 289260
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 440ce1b4fc4..bdbce8a9dac 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1211,14 +1211,15 @@ unsigned SIRegisterInfo::getMinNumSGPRs(const SISubtarget &ST, } unsigned SIRegisterInfo::getMaxNumSGPRs(const SISubtarget &ST, - unsigned WavesPerEU) const { + unsigned WavesPerEU, + bool Addressable) const { if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { switch (WavesPerEU) { case 0: return 80; case 10: return 80; case 9: return 80; case 8: return 96; - default: return getNumAddressableSGPRs(ST); + default: return Addressable ? getNumAddressableSGPRs(ST) : 112; } } else { switch (WavesPerEU) { @@ -1243,7 +1244,8 @@ unsigned SIRegisterInfo::getMaxNumSGPRs(const MachineFunction &MF) const { // Compute maximum number of SGPRs function can use using default/requested // minimum number of waves per execution unit. std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU(); - unsigned MaxNumSGPRs = getMaxNumSGPRs(ST, WavesPerEU.first); + unsigned MaxNumSGPRs = getMaxNumSGPRs(ST, WavesPerEU.first, false); + unsigned MaxNumAddressableSGPRs = getMaxNumSGPRs(ST, WavesPerEU.first, true); // Check if maximum number of SGPRs was explicitly requested using // "amdgpu-num-sgpr" attribute. @@ -1268,7 +1270,7 @@ unsigned SIRegisterInfo::getMaxNumSGPRs(const MachineFunction &MF) const { // Make sure requested value is compatible with values implied by // default/requested minimum/maximum number of waves per execution unit. - if (Requested && Requested > getMaxNumSGPRs(ST, WavesPerEU.first)) + if (Requested && Requested > getMaxNumSGPRs(ST, WavesPerEU.first, false)) Requested = 0; if (WavesPerEU.second && Requested && Requested < getMinNumSGPRs(ST, WavesPerEU.second)) @@ -1281,7 +1283,7 @@ unsigned SIRegisterInfo::getMaxNumSGPRs(const MachineFunction &MF) const { if (ST.hasSGPRInitBug()) MaxNumSGPRs = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG; - return MaxNumSGPRs - getNumReservedSGPRs(ST); + return std::min(MaxNumSGPRs - getNumReservedSGPRs(ST), MaxNumAddressableSGPRs); } unsigned SIRegisterInfo::getNumDebuggerReservedVGPRs( |
