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| author | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:54 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:54 +0000 |
| commit | 0f55fbae6c7f40938b27571a20752a376ae49eb1 (patch) | |
| tree | 528ef08804bc9a7243957b77561bef09bacbb01b /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 693e9be9181eb8b3cc91e254a2acb49accafbd9c (diff) | |
| download | bcm5719-llvm-0f55fbae6c7f40938b27571a20752a376ae49eb1.tar.gz bcm5719-llvm-0f55fbae6c7f40938b27571a20752a376ae49eb1.zip | |
AMDGPU/SI: Don't reserve XNACK when it's disabled
Summary:
This frees 2 additional scalar registers.
These are results from all of my 3 patches combined:
Polaris:
Spilled SGPRs: 2231 -> 1517 (-32.00 %)
Tonga:
Spilled SGPRs: 3829 -> 2608 (-31.89 %)
Spilled VGPRs: 100 -> 84 (-16.00 %)
Tonga even spills SGPRs via VGPRs to scratch. That's a compute shader
limited to 64 VGPRs.
Reviewers: tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27151
llvm-svn: 289262
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 0fdd203b3d0..41633a2b6a0 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1188,7 +1188,7 @@ unsigned SIRegisterInfo::getNumReservedSGPRs(const SISubtarget &ST, return 4; // FLAT_SCRATCH, VCC (in that order) } - if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) + if (ST.isXNACKEnabled()) return 4; // XNACK, VCC (in that order) return 2; // VCC. |
