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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-04-24 19:37:54 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-04-24 19:37:54 +0000 |
| commit | bd5394be3d2b33cfc9ea396f99967d48647763a6 (patch) | |
| tree | 7764a63b902c320511d9fe6a53772cad34d26841 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 610c966a4e90775860e9c3eb91efbd6b1e0dd28b (diff) | |
| download | bcm5719-llvm-bd5394be3d2b33cfc9ea396f99967d48647763a6.tar.gz bcm5719-llvm-bd5394be3d2b33cfc9ea396f99967d48647763a6.zip | |
[AMDGPU] Merge M0 initializations
Merges equivalent initializations of M0 and hoists them into a common
dominator block. Technically the same code can be used with any
register, physical or virtual.
Differential Revision: https://reviews.llvm.org/D32279
llvm-svn: 301228
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index f2fdf96c42e..8820e294562 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -146,6 +146,9 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { reserveRegisterTuples(Reserved, AMDGPU::EXEC); reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); + // M0 has to be reserved so that llvm accepts it as a live-in into a block. + reserveRegisterTuples(Reserved, AMDGPU::M0); + // Reserve the memory aperture registers. reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); |
