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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-18 18:29:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-18 18:29:53 +0000 |
| commit | e823d92f7fb170d40d8c40e062accd398b60d2f6 (patch) | |
| tree | f3cc1d6ef3753fb31c10d674574f90899fabdfd6 /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | 6d5dddb85f6a45be8f5e3b8f25adf4a0dbfc159c (diff) | |
| download | bcm5719-llvm-e823d92f7fb170d40d8c40e062accd398b60d2f6.tar.gz bcm5719-llvm-e823d92f7fb170d40d8c40e062accd398b60d2f6.zip | |
AMDGPU: Merge initial gfx9 support
llvm-svn: 295554
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 00394623db4..a90fc28ced3 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -133,6 +133,12 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { reserveRegisterTuples(Reserved, AMDGPU::EXEC); reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); + // Reserve the memory aperture registers. + reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); + reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); + reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); + reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); + // Reserve Trap Handler registers - support is not implemented in Codegen. reserveRegisterTuples(Reserved, AMDGPU::TBA); reserveRegisterTuples(Reserved, AMDGPU::TMA); |
