Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Added partselect example | Rodrigo Alejandro Melo | 2017-11-23 | 1 | -0/+27 |
| | | | | The conversion to Verilog must be fixed. | ||||
* | Allow second argument to CONVFUNC_2 to be expr | Larry Doolittle | 2017-11-22 | 1 | -1/+1 |
| | | | | | Adds one more shift/reduce conflict. Include test case. | ||||
* | Experimental support of exponentiation | Rodrigo Alejandro Melo | 2017-11-21 | 1 | -0/+4 |
| | |||||
* | Adding support for while loop | Larry Doolittle | 2017-11-20 | 1 | -0/+26 |
| | | | | | Supplied by jeinstei Labelling of the loop is still unsupported. | ||||
* | Simple fix to genericmap example | Larry Doolittle | 2017-11-18 | 1 | -2/+2 |
| | |||||
* | Fix capitalization of iverilog | Larry Doolittle | 2017-11-17 | 1 | -1/+1 |
| | |||||
* | Modified the Makefile to run GHDl and iVerilog always but only if installed | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -0/+14 |
| | |||||
* | Removed extra parentheses when parentheses are used | Rodrigo Alejandro Melo | 2017-11-17 | 2 | -2/+2 |
| | |||||
* | Removed unuseful parentheses | Rodrigo Alejandro Melo | 2017-11-17 | 8 | -39/+39 |
| | |||||
* | Parentheses were removed for CONVFUNC_1 (ex. to_integer) | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -2/+2 |
| | |||||
* | Added (partial) support for to_integer function | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
| | | | | Added an example that fail to todo.vhd. | ||||
* | Changes on genericmap due to unsupported port assignment | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
| | | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd. | ||||
* | Changes on translated_examples (dsp and ifchain2) due to previous changes in ↵ | Rodrigo Alejandro Melo | 2017-11-16 | 2 | -2/+2 |
| | | | | examples | ||||
* | Squelch some trailing whitespace | Larry Doolittle | 2017-11-12 | 1 | -4/+4 |
| | |||||
* | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 4 | -4/+83 |
| | |||||
* | New make target: verilogcheck | Larry Doolittle | 2017-11-10 | 2 | -0/+25 |
| | | | | | | | Requires iverilog to operate. Scans resulting files in translated_examples directory. This patch includes some simple fixes to reduce the number of errors reported, but there are more that need further investigation. | ||||
* | New rem before END PROCESS | Larry Doolittle | 2017-11-10 | 1 | -0/+36 |
| | | | | With test case! | ||||
* | Experiment with OTHERS logic | Larry Doolittle | 2017-11-09 | 1 | -0/+16 |
| | | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code! | ||||
* | Fixes in examples and translated examples to avoid some complains of iVerilog | Rodrigo Alejandro Melo | 2017-02-19 | 4 | -8/+7 |
| | | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog. | ||||
* | Promoted unsupported BASED NUMBER from warning to error | Rodrigo Alejandro Melo | 2017-02-19 | 1 | -1/+1 |
| | | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed. | ||||
* | Modified to use ',' to separate sensitivity list in verilog 2001 | Rodrigo Alejandro Melo | 2017-02-17 | 7 | -19/+19 |
| | | | | Changes applied to translated_examples. | ||||
* | Changed translated_examples due that Verilog 2001 is now the default | Rodrigo Alejandro Melo | 2017-02-17 | 13 | -455/+162 |
| | |||||
* | Added command line option --quiet | Rodrigo Alejandro Melo | 2017-02-17 | 13 | -273/+0 |
| | | | | | Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples. | ||||
* | Added analysis of examples with GHDL | Rodrigo Alejandro Melo | 2017-02-14 | 5 | -14/+14 |
| | | | | | | | | Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented. | ||||
* | Added scientific notation supports for integers and floats | Rodrigo Alejandro Melo | 2017-02-09 | 1 | -0/+36 |
| | | | | | Also support was added for real numbers especially thinking in generics. Files called scientific.vhd and scientific.v were added for test. | ||||
* | Space deleted in the <size>'<radix><number> notation | Rodrigo Alejandro Melo | 2017-02-09 | 11 | -246/+246 |
| | | | | | | | It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified. | ||||
* | vhd2vl-2.5 | Larry Doolittle | 2015-09-20 | 12 | -24/+24 |
| | |||||
* | vhd2vl-2.4 | Larry Doolittle | 2015-09-20 | 12 | -68/+107 |
| | |||||
* | vhd2vl-2.3 | Larry Doolittle | 2015-09-20 | 12 | -22/+244 |
| | |||||
* | vhd2vl-2.2 | Larry Doolittle | 2015-09-20 | 11 | -0/+1727 |