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* Fixed partselect exampleRodrigo Alejandro Melo2017-11-262-3/+3
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* Correct selection of -: vs. +:Larry Doolittle2017-11-257-38/+45
| | | | | Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd
* Add missing CONVFUNC_1 to grammarLarry Doolittle2017-11-243-2/+7
| | | | Allows completion of dsp.vhd changes from previous commit
* Fixed dsp.vhdRodrigo Alejandro Melo2017-11-241-13/+15
| | | | There is a new problem (commented).
* Turn off debug prints and fix warningsLarry Doolittle2017-11-235-14/+30
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* First stupid attempt to finish part selectLarry Doolittle2017-11-239-49/+67
| | | | | No attempt to figure out -: vs. +: Already yields much better results on test files
* Fill in size_expr with reduced diffLarry Doolittle2017-11-231-22/+26
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* Added partselect exampleRodrigo Alejandro Melo2017-11-232-0/+57
| | | | The conversion to Verilog must be fixed.
* Experiment towards indexed part selectLarry Doolittle2017-11-231-5/+90
| | | | No change in stdout, just lots of chatter on stderr
* Allow second argument to CONVFUNC_2 to be exprLarry Doolittle2017-11-223-4/+4
| | | | | Adds one more shift/reduce conflict. Include test case.
* Merge branch 'exponentiation'Larry Doolittle2017-11-224-2/+19
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| * Supports for exponentiation at the lex layerRodrigo Alejandro Melo2017-11-222-4/+6
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| * Experimental support of exponentiationRodrigo Alejandro Melo2017-11-213-1/+16
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* | Improve c89 compatibilityLarry Doolittle2017-11-211-9/+9
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* Add development hook for visualising slistsLarry Doolittle2017-11-201-0/+48
| | | | Use case is disabled, so no default effect.
* Adding support for while loopLarry Doolittle2017-11-204-1/+69
| | | | | Supplied by jeinstei Labelling of the loop is still unsupported.
* Align the prototypes for dsp in dsp and genericmapLarry Doolittle2017-11-202-4/+3
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* Beginning support for assertionsLarry Doolittle2017-11-183-0/+26
| | | | Based on work by jeinstei
* Simple fix to genericmap exampleLarry Doolittle2017-11-182-4/+4
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* Fix capitalization of iverilogLarry Doolittle2017-11-171-1/+1
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* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-173-15/+28
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* Removed extra parentheses when parentheses are usedRodrigo Alejandro Melo2017-11-173-3/+4
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* Removed unuseful parenthesesRodrigo Alejandro Melo2017-11-179-40/+40
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* Fixed rebuild of vhd2vl in the main MakefileRodrigo Alejandro Melo2017-11-171-7/+4
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* Used addnest function to replace code for BITVECTRodrigo Alejandro Melo2017-11-171-9/+2
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* Parentheses were removed for CONVFUNC_1 (ex. to_integer)Rodrigo Alejandro Melo2017-11-172-4/+4
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* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-163-4/+9
| | | | Added an example that fail to todo.vhd.
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-163-7/+26
| | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd.
* The resulting files of the GHDL analysis were moved to temp/vhdlRodrigo Alejandro Melo2017-11-161-2/+5
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* Added the special file examples/todo.vhdRodrigo Alejandro Melo2017-11-162-2/+25
| | | | | | The idea is to put there things that don't work or that could be improved. Is ignored in the main Makefile when target 'translate' is used. The target 'todo' was added to the main Makefile.
* Changes on translated_examples (dsp and ifchain2) due to previous changes in ↵Rodrigo Alejandro Melo2017-11-162-2/+2
| | | | examples
* Examples were corrected according to GHDL complainsRodrigo Alejandro Melo2017-11-165-8/+10
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* Updates to CHANGELOG.mdLarry Doolittle2017-11-131-1/+17
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* Squelch some trailing whitespaceLarry Doolittle2017-11-125-21/+20
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* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-109-12/+178
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* New make target: verilogcheckLarry Doolittle2017-11-105-0/+52
| | | | | | | Requires iverilog to operate. Scans resulting files in translated_examples directory. This patch includes some simple fixes to reduce the number of errors reported, but there are more that need further investigation.
* New rem before END PROCESSLarry Doolittle2017-11-103-5/+73
| | | | With test case!
* Experiment with OTHERS logicLarry Doolittle2017-11-093-14/+44
| | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code!
* Makefile adjustmentsLarry Doolittle2017-11-091-3/+8
| | | | | Allow people without GHDL installed to make the diff target Make it clear when the diff target succeeds
* use enum for slist typeLarry Doolittle2017-11-092-22/+33
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* one more rem in generic patternLarry Doolittle2017-11-091-4/+4
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* Merge branch 'rodrigomelo9-master'Larry Doolittle2017-11-0934-1139/+700
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| * Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-198-22/+21
| | | | | | | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog.
| * Improved WARNING messages indicationRodrigo Alejandro Melo2017-02-191-18/+14
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| * Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-193-6/+7
| | | | | | | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed.
| * Fixed warnig in vhd2vl.y introduced in the previous commitRodrigo Alejandro Melo2017-02-171-9/+7
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| * Modified to use ',' to separate sensitivity list in verilog 2001Rodrigo Alejandro Melo2017-02-178-22/+31
| | | | | | | | Changes applied to translated_examples.
| * Changed translated_examples due that Verilog 2001 is now the defaultRodrigo Alejandro Melo2017-02-1713-455/+162
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| * Updated version and how to use in README.mdRodrigo Alejandro Melo2017-02-171-44/+41
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| * Changed vhd2vl version to 3.0Rodrigo Alejandro Melo2017-02-171-2/+4
| | | | | | | | Added Rodrigo A. Melo as contributor.
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