Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Fixed partselect example | Rodrigo Alejandro Melo | 2017-11-26 | 2 | -3/+3 |
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* | Correct selection of -: vs. +: | Larry Doolittle | 2017-11-25 | 7 | -38/+45 |
| | | | | | Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd | ||||
* | Add missing CONVFUNC_1 to grammar | Larry Doolittle | 2017-11-24 | 3 | -2/+7 |
| | | | | Allows completion of dsp.vhd changes from previous commit | ||||
* | Fixed dsp.vhd | Rodrigo Alejandro Melo | 2017-11-24 | 1 | -13/+15 |
| | | | | There is a new problem (commented). | ||||
* | Turn off debug prints and fix warnings | Larry Doolittle | 2017-11-23 | 5 | -14/+30 |
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* | First stupid attempt to finish part select | Larry Doolittle | 2017-11-23 | 9 | -49/+67 |
| | | | | | No attempt to figure out -: vs. +: Already yields much better results on test files | ||||
* | Fill in size_expr with reduced diff | Larry Doolittle | 2017-11-23 | 1 | -22/+26 |
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* | Added partselect example | Rodrigo Alejandro Melo | 2017-11-23 | 2 | -0/+57 |
| | | | | The conversion to Verilog must be fixed. | ||||
* | Experiment towards indexed part select | Larry Doolittle | 2017-11-23 | 1 | -5/+90 |
| | | | | No change in stdout, just lots of chatter on stderr | ||||
* | Allow second argument to CONVFUNC_2 to be expr | Larry Doolittle | 2017-11-22 | 3 | -4/+4 |
| | | | | | Adds one more shift/reduce conflict. Include test case. | ||||
* | Merge branch 'exponentiation' | Larry Doolittle | 2017-11-22 | 4 | -2/+19 |
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| * | Supports for exponentiation at the lex layer | Rodrigo Alejandro Melo | 2017-11-22 | 2 | -4/+6 |
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| * | Experimental support of exponentiation | Rodrigo Alejandro Melo | 2017-11-21 | 3 | -1/+16 |
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* | | Improve c89 compatibility | Larry Doolittle | 2017-11-21 | 1 | -9/+9 |
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* | Add development hook for visualising slists | Larry Doolittle | 2017-11-20 | 1 | -0/+48 |
| | | | | Use case is disabled, so no default effect. | ||||
* | Adding support for while loop | Larry Doolittle | 2017-11-20 | 4 | -1/+69 |
| | | | | | Supplied by jeinstei Labelling of the loop is still unsupported. | ||||
* | Align the prototypes for dsp in dsp and genericmap | Larry Doolittle | 2017-11-20 | 2 | -4/+3 |
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* | Beginning support for assertions | Larry Doolittle | 2017-11-18 | 3 | -0/+26 |
| | | | | Based on work by jeinstei | ||||
* | Simple fix to genericmap example | Larry Doolittle | 2017-11-18 | 2 | -4/+4 |
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* | Fix capitalization of iverilog | Larry Doolittle | 2017-11-17 | 1 | -1/+1 |
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* | Modified the Makefile to run GHDl and iVerilog always but only if installed | Rodrigo Alejandro Melo | 2017-11-17 | 3 | -15/+28 |
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* | Removed extra parentheses when parentheses are used | Rodrigo Alejandro Melo | 2017-11-17 | 3 | -3/+4 |
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* | Removed unuseful parentheses | Rodrigo Alejandro Melo | 2017-11-17 | 9 | -40/+40 |
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* | Fixed rebuild of vhd2vl in the main Makefile | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -7/+4 |
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* | Used addnest function to replace code for BITVECT | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -9/+2 |
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* | Parentheses were removed for CONVFUNC_1 (ex. to_integer) | Rodrigo Alejandro Melo | 2017-11-17 | 2 | -4/+4 |
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* | Added (partial) support for to_integer function | Rodrigo Alejandro Melo | 2017-11-16 | 3 | -4/+9 |
| | | | | Added an example that fail to todo.vhd. | ||||
* | Changes on genericmap due to unsupported port assignment | Rodrigo Alejandro Melo | 2017-11-16 | 3 | -7/+26 |
| | | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd. | ||||
* | The resulting files of the GHDL analysis were moved to temp/vhdl | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+5 |
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* | Added the special file examples/todo.vhd | Rodrigo Alejandro Melo | 2017-11-16 | 2 | -2/+25 |
| | | | | | | The idea is to put there things that don't work or that could be improved. Is ignored in the main Makefile when target 'translate' is used. The target 'todo' was added to the main Makefile. | ||||
* | Changes on translated_examples (dsp and ifchain2) due to previous changes in ↵ | Rodrigo Alejandro Melo | 2017-11-16 | 2 | -2/+2 |
| | | | | examples | ||||
* | Examples were corrected according to GHDL complains | Rodrigo Alejandro Melo | 2017-11-16 | 5 | -8/+10 |
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* | Updates to CHANGELOG.md | Larry Doolittle | 2017-11-13 | 1 | -1/+17 |
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* | Squelch some trailing whitespace | Larry Doolittle | 2017-11-12 | 5 | -21/+20 |
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* | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 9 | -12/+178 |
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* | New make target: verilogcheck | Larry Doolittle | 2017-11-10 | 5 | -0/+52 |
| | | | | | | | Requires iverilog to operate. Scans resulting files in translated_examples directory. This patch includes some simple fixes to reduce the number of errors reported, but there are more that need further investigation. | ||||
* | New rem before END PROCESS | Larry Doolittle | 2017-11-10 | 3 | -5/+73 |
| | | | | With test case! | ||||
* | Experiment with OTHERS logic | Larry Doolittle | 2017-11-09 | 3 | -14/+44 |
| | | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code! | ||||
* | Makefile adjustments | Larry Doolittle | 2017-11-09 | 1 | -3/+8 |
| | | | | | Allow people without GHDL installed to make the diff target Make it clear when the diff target succeeds | ||||
* | use enum for slist type | Larry Doolittle | 2017-11-09 | 2 | -22/+33 |
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* | one more rem in generic pattern | Larry Doolittle | 2017-11-09 | 1 | -4/+4 |
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* | Merge branch 'rodrigomelo9-master' | Larry Doolittle | 2017-11-09 | 34 | -1139/+700 |
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| * | Fixes in examples and translated examples to avoid some complains of iVerilog | Rodrigo Alejandro Melo | 2017-02-19 | 8 | -22/+21 |
| | | | | | | | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog. | ||||
| * | Improved WARNING messages indication | Rodrigo Alejandro Melo | 2017-02-19 | 1 | -18/+14 |
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| * | Promoted unsupported BASED NUMBER from warning to error | Rodrigo Alejandro Melo | 2017-02-19 | 3 | -6/+7 |
| | | | | | | | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed. | ||||
| * | Fixed warnig in vhd2vl.y introduced in the previous commit | Rodrigo Alejandro Melo | 2017-02-17 | 1 | -9/+7 |
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| * | Modified to use ',' to separate sensitivity list in verilog 2001 | Rodrigo Alejandro Melo | 2017-02-17 | 8 | -22/+31 |
| | | | | | | | | Changes applied to translated_examples. | ||||
| * | Changed translated_examples due that Verilog 2001 is now the default | Rodrigo Alejandro Melo | 2017-02-17 | 13 | -455/+162 |
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| * | Updated version and how to use in README.md | Rodrigo Alejandro Melo | 2017-02-17 | 1 | -44/+41 |
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| * | Changed vhd2vl version to 3.0 | Rodrigo Alejandro Melo | 2017-02-17 | 1 | -2/+4 |
| | | | | | | | | Added Rodrigo A. Melo as contributor. |