Merge branch 'exponentiation'

4 files changed, 19 insertions, 2 deletions

diff --git a/examples/expr.vhd b/examples/expr.vhd
index 81e8ab1..827c433 100644
--- a/examples/expr.vhd
+++ b/examples/expr.vhd
@@ -2,15 +2,20 @@ library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-entity expr is port( reset, sysclk, ival : in std_logic);
+entity expr is
+generic(SIZE: positive:=2**8-1);
+port(reset, sysclk, ival : in std_logic);
 end expr;
+
 architecture rtl of expr is
+  constant SIZE_OF : positive:=2**8-1;
   signal foo : std_logic_vector(13 downto 0);
   signal baz : std_logic_vector(2 downto 0);
   signal bam : std_logic_vector(22 downto 0);
   signal out_i : std_logic_vector(5 downto 3);
   signal input_status : std_logic_vector(8 downto 0);
   signal enable, debug, aux, outy, dv, value : std_logic;
+  signal expo : std_logic_vector(2**3-1 downto 0);
 begin
   -- drive input status
   input_status <=    -- top bits
@@ -36,4 +41,6 @@ begin
       bam(foo'range) <= foo;
     end if;
   end process;
+
+  --expo <= std_logic_vector(to_unsigned(2**4, 2**8));
 end rtl;
diff --git a/src/vhd2vl.l b/src/vhd2vl.l
index d2cda55..b4de189 100644
--- a/src/vhd2vl.l
+++ b/src/vhd2vl.l
@@ -122,6 +122,7 @@ void getbasedstring(unsigned skip);
 "xor" { return XOR; }
 "xnor" { return XNOR; }
 "mod" { return MOD; }
+"**" { return POW; }
 "event" { return EVENT; }
 "rising_edge" { return POSEDGE;}
 "falling_edge" { return NEGEDGE;}
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index 2168073..f0efb24 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -740,7 +740,7 @@ slist *emit_io_list(slist *sl)
 %token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT
 %token <txt> IF THEN ELSIF ELSE CASE WHILE
 %token <txt> FOR LOOP GENERATE
-%token <txt> AFTER AND OR XOR MOD
+%token <txt> AFTER AND OR XOR MOD POW
 %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
 %token <txt> STRING NAME RANGE NULLV OPEN
 %token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT LEFT
@@ -784,6 +784,7 @@ slist *emit_io_list(slist *sl)
 %left '<'  '>'  BIGEQ  LESSEQ  NOTEQ  EQUAL
 %left  '+'  '-'  '&'
 %left  '*'  '/'
+%left  POW
 %right UMINUS  UPLUS  NOTL  NOT
 %error-verbose
 
@@ -2219,6 +2220,7 @@ expr : signal {
      | '+' expr %prec UPLUS {$$=addexpr(NULL,'p'," +",$2);}
      | expr '+' expr {$$=addexpr($1,'+'," + ",$3);}
      | expr '-' expr {$$=addexpr($1,'-'," - ",$3);}
+     | expr POW expr {$$=addexpr($1,'*'," ** ",$3);}
      | expr '*' expr {$$=addexpr($1,'*'," * ",$3);}
      | expr '/' expr {$$=addexpr($1,'/'," / ",$3);}
      | expr MOD expr {$$=addexpr($1,'%'," % ",$3);}
@@ -2415,6 +2417,9 @@ simple_expr : signal {
      | simple_expr '-' simple_expr {
        $$=addexpr($1,'-'," - ",$3);
       }
+     | simple_expr POW simple_expr {
+       $$=addexpr($1,'*'," ** ",$3);
+      }
      | simple_expr '*' simple_expr {
        $$=addexpr($1,'*'," * ",$3);
       }
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index cf4fd53..d6691ea 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -6,15 +6,18 @@ input wire sysclk,
 input wire ival
 );
 
+parameter [31:0] SIZE=2 ** 8 - 1;
 
 
 
+parameter SIZE_OF = 2 ** 8 - 1;
 reg [13:0] foo;
 wire [2:0] baz;
 reg [22:0] bam;
 wire [5:3] out_i;
 wire [8:0] input_status;
 wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
+wire [2 ** 3 - 1:0] expo;
 
   // drive input status
   assign input_status = {foo[9:4],(baz[2:0] & foo[3:0]) | ( ~baz[2:0] & bam[3:0])};
@@ -30,5 +33,6 @@ wire enable; wire debug; wire aux; wire outy; wire dv; wire value;
     end
   end
 
+    //expo <= std_logic_vector(to_unsigned(2**4, 2**8));
 
 endmodule