First stupid attempt to finish part select

No attempt to figure out -: vs. +:
Already yields much better results on test files

9 files changed, 67 insertions, 49 deletions

diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
index 3fc1d9d..cdaf51f 100644
--- a/examples/bigfile.vhd
+++ b/examples/bigfile.vhd
@@ -227,7 +227,7 @@ begin
               -- set
               g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
             else
-              exit;
+              -- XXX not ready for exit;
             end if;
           --vnavigatoroff
           else
diff --git a/examples/dsp.vhd b/examples/dsp.vhd
index 7eda7c1..4f139d5 100644
--- a/examples/dsp.vhd
+++ b/examples/dsp.vhd
@@ -25,8 +25,15 @@ end;
 
 architecture rtl of dsp is
     signal foo : std_logic;
+    signal sr : std_logic_vector(63 downto 0);
 begin
     process(clk) begin
-       dout <= std_logic_vector(to_unsigned(1,bus_width));
+       -- dout <= std_logic_vector(to_unsigned(1,bus_width));
+       if rising_edge(clk) then
+           if we = '1' then
+               sr <= sr(thing_size-bus_width-1 downto 0) & din;
+           end if;
+           dout <= sr(param*bus_width+bus_width-1 downto param*bus_width);
+       end if;
     end process;
 end rtl;
diff --git a/examples/for.vhd b/examples/for.vhd
index c18c2e3..71ff3a5 100644
--- a/examples/for.vhd
+++ b/examples/for.vhd
@@ -12,7 +12,7 @@ architecture rtl of forp is
 begin
   TIMERS :
   process(reset, sysclk)
-    variable timer_var : integer:= 0;
+    variable timer_var : integer; -- XXX unhandled := 0;
     variable a, i, j, k : integer;
     variable zz5 : std_logic_vector(31 downto 0);
     variable zz : std_logic_vector(511 downto 0);
diff --git a/examples/partselect.vhd b/examples/partselect.vhd
index 14b6520..25279dd 100644
--- a/examples/partselect.vhd
+++ b/examples/partselect.vhd
@@ -15,14 +15,14 @@ begin
 
    test_i: process(clk_i)
       variable big_var : std_logic_vector(31 downto 0);
-      variable j       : integer:=8;
+      variable j       : integer; -- XXX not ready for :=8;
    begin
       if rising_edge(clk_i) then
          big_sig(31 downto 24) <= big_sig(7 downto 0);
          big_var(31 downto 24) := big_var(7 downto 0);
          lit_sig(24 to 31)     <= lit_sig(0 to 7);
          --
-         big_sig(i*3+8 downto i*3) <= big_sig(i-1 downto 0);
+         big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0);
          big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0);
       end if;
    end process test_i;
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index be3102c..46deefc 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -302,30 +302,33 @@ slist *addind(slist *sl){
   return sl;
 }
 
-slist *addpar(slist *sl, vrange *v){
+slist *addpar_snug(slist *sl, vrange *v){
+  fprintf(stderr,"addpar_snug %d: ", v->sizeval);
+  fslprint(stderr, v->size_expr);
+  fprintf(stderr,"\n");
   if(v->nlo != NULL) {   /* indexes are simple expressions */
-    sl=addtxt(sl," [");
+    sl=addtxt(sl,"[");
     if(v->nhi != NULL){
       sl=addsl(sl,v->nhi);
+      if(v->sizeval==-2) sl=addtxt(sl,"+");
       sl=addtxt(sl,":");
     }
-    sl=addsl(sl,v->nlo);
-    sl=addtxt(sl,"] ");
-  } else {
-    sl=addtxt(sl," ");
+    if(v->sizeval==-2){
+      sl=addsl(sl,v->size_expr);
+      sl=addtxt(sl," + 1");
+    } else {
+      sl=addsl(sl,v->nlo);
+    }
+    sl=addtxt(sl,"]");
   }
   return sl;
 }
 
-slist *addpar_snug(slist *sl, vrange *v){
+slist *addpar(slist *sl, vrange *v){
+  sl=addtxt(sl," ");
   if(v->nlo != NULL) {   /* indexes are simple expressions */
-    sl=addtxt(sl,"[");
-    if(v->nhi != NULL){
-      sl=addsl(sl,v->nhi);
-      sl=addtxt(sl,":");
-    }
-    sl=addsl(sl,v->nlo);
-    sl=addtxt(sl,"]");
+    sl=addpar_snug(sl, v);
+    sl=addtxt(sl," ");
   }
   return sl;
 }
@@ -1219,6 +1222,7 @@ vec_range : simple_expr updown simple_expr {
                 }
               } else if ((range_diff = slist_check_diff($$->nhi, $$->nlo))) {
                 if (DEBUG_RANGE) fprintf(stderr, "difference: %s\n", range_diff);
+                $$->sizeval = -2;  /* special */
                 $$->size_expr = addtxt(NULL, range_diff);
               } else {
                 /* make an expression to calculate the width of this vrange:
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index 36dfdb8..ff4e56d 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -175,7 +175,7 @@ wire [31:0] g_dout_i;
               g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b1};
             end
             else begin
-              disable;  //VHD2VL: add block name here
+              // XXX not ready for exit;
             end
             //vnavigatoroff
           end
@@ -185,7 +185,7 @@ wire [31:0] g_dout_i;
           //vnavigatoron
           case(g_dout_w0x0f_v)
           g_t_klim_w0x0f : begin
-            g_t_klim_dout <= din[i * 32 + 31:i * 32];
+            g_t_klim_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_t_u_w0x0f : begin
             // output klim
@@ -196,68 +196,68 @@ wire [31:0] g_dout_i;
             end
           end
           g_t_l_w0x0f : begin
-            g_t_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_t_hhh_l_w0x0f : begin
-            g_t_hhh_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_hhh_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_t_jkl_sink_l_w0x0f : begin
-            g_t_jkl_sink_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_jkl_sink_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_secondary_t_l_w0x0f : begin
-            g_secondary_t_l_dout <= din[i * 32 + 31:i * 32];
+            g_secondary_t_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_style_c_l_w0x0f : begin
-            g_style_c_l_dout[3:0] <= din[3 + i * 32:i * 32];
+            g_style_c_l_dout[3:0] <= din[3 + i * 32+:3 + 1];
           end
           g_e_z_w0x0f : begin
-            g_e_z_dout <= din[i * 32 + 31:i * 32];
+            g_e_z_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_n_both_qbars_l_w0x0f : begin
-            g_n_both_qbars_l_dout <= din[i * 32 + 31:i * 32];
+            g_n_both_qbars_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_style_vfr_w0x0f : begin
             // read-only register
           end
           g_style_klim_w0x0f : begin
-            g_style_klim_dout <= din[i * 32 + 31:i * 32];
+            g_style_klim_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_unklimed_style_vfr_w0x0f : begin
             // read-only register
           end
           g_style_t_y_w0x0f : begin
-            g_style_t_y_dout <= din[i * 32 + 31:i * 32];
+            g_style_t_y_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_n_l_w0x0f : begin
-            g_n_l_dout <= din[i * 32 + 31:i * 32];
+            g_n_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_n_vfr_w0x0f : begin
             // writes
           end
           g_e_n_r_w0x0f : begin
-            g_e_n_r_dout <= din[i * 32 + 31:i * 32];
+            g_e_n_r_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_n_r_bne_w0x0f : begin
             g_n_r_bne_dout <= din[i * 32];
           end
           g_n_div_rebeq_w0x0f : begin
-            g_n_div_rebeq_dout <= din[i * 32 + 31:i * 32] | g_n_div_rebeq_dout;
+            g_n_div_rebeq_dout <= din[i * 32 + 31+:31 + 1] | g_n_div_rebeq_dout;
             // a '1' writes
           end
           g_alu_l_w0x0f : begin
-            g_alu_l_dout <= din[i * 32 + 31:i * 32];
+            g_alu_l_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_t_qaz_mult_low_w0x0f : begin
-            g_t_qaz_mult_low_dout <= din[i * 32 + 31:i * 32];
+            g_t_qaz_mult_low_dout <= din[i * 32 + 31+:31 + 1];
           end
           g_t_qaz_mult_high_w0x0f : begin
-            g_t_qaz_mult_high_dout <= din[i * 32 + 31:i * 32];
+            g_t_qaz_mult_high_dout <= din[i * 32 + 31+:31 + 1];
           end
           gwerthernal_style_u_w0x0f : begin
-            gwerthernal_style_u_dout <= din[i * 32 + 31:i * 32];
+            gwerthernal_style_u_dout <= din[i * 32 + 31+:31 + 1];
           end
           gwerthernal_style_l_w0x0f : begin
-            gwerthernal_style_l_dout <= din[i * 32 + 31:i * 32];
+            gwerthernal_style_l_dout <= din[i * 32 + 31+:31 + 1];
             //vnavigatoroff                                                          
           end
           default : begin
@@ -397,15 +397,15 @@ wire [31:0] g_dout_i;
       idiv8 = i / 8;
       if((g_n_r_bne_dout == 1'b0)) begin
         // non-unique
-        g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
+        g_vector[8 * i + 7+:7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7+:7 + 1];
       end
       else begin
         // unique
         if((imod8 == 0)) begin
-          g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
+          g_vector[8 * i + 7+:7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7+:7 + 1];
         end
         else begin
-          g_vector[8 * i + 7:8 * i] <= (g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8]) + (imod8);
+          g_vector[8 * i + 7+:7 + 1] <= (g_e_n_r_dout[8 * idiv8 + 7+:7 + 1]) + (imod8);
         end
       end
     end
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v
index 52474d3..24b3626 100644
--- a/translated_examples/dsp.v
+++ b/translated_examples/dsp.v
@@ -25,9 +25,14 @@ parameter [31:0] bus_width=24;
 
 
 wire foo;
-
-  always @(clk) begin
-    dout <= 1;
+reg [63:0] sr;
+
+  always @(posedge clk) begin
+      // dout <= std_logic_vector(to_unsigned(1,bus_width));
+    if(we == 1'b1) begin
+      sr <= {sr[thing_size - bus_width - 1:0],din};
+    end
+    dout <= sr[param * bus_width + bus_width - 1+:bus_width - 1 + 1];
   end
 
 
diff --git a/translated_examples/for.v b/translated_examples/for.v
index 0c00762..707d981 100644
--- a/translated_examples/for.v
+++ b/translated_examples/for.v
@@ -12,7 +12,8 @@ reg selection;
 reg [6:0] egg_timer;
 
   always @(posedge reset, posedge sysclk) begin : P1
-    reg [31:0] timer_var = 0;
+    reg [31:0] timer_var;
+  // XXX unhandled := 0;
     reg [31:0] a, i, j, k;
     reg [31:0] zz5;
     reg [511:0] zz;
@@ -28,7 +29,7 @@ reg [6:0] egg_timer;
       for (i=0; i <= j * k; i = i + 1) begin
         a = a + i;
         for (k=a - 9; k >=  -14; k = k - 1) begin
-          zz5 = zz[31 + k:k];
+          zz5 = zz[31 + k+:31 + 1];
         end
         // k
       end
diff --git a/translated_examples/partselect.v b/translated_examples/partselect.v
index 9eba2a8..2197b0b 100644
--- a/translated_examples/partselect.v
+++ b/translated_examples/partselect.v
@@ -13,14 +13,15 @@ wire [31:0] i = 8;
 
   always @(posedge clk_i) begin : P1
     reg [31:0] big_var;
-    reg [31:0] j = 8;
+    reg [31:0] j;
+  // XXX not ready for :=8;
 
     big_sig[31:24] <= big_sig[7:0];
     big_var[31:24] = big_var[7:0];
     lit_sig[24:31] <= lit_sig[0:7];
     //
-    big_sig[i * 3 + 8:i * 3] <= big_sig[i - 1:0];
-    big_var[j * 3 + 8:j * 3] = big_var[j * 0 + 8:j * 0];
+    big_sig[i * 3 + 8+:8 + 1] <= big_sig[8:0];
+    big_var[j * 3 + 8+:8 + 1] = big_var[j * 0 + 8+:8 + 1];
   end