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talos-sbe
04-16-2019
07-25-2019
master
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p9
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procedures
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hwp
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perv
Commit message (
Expand
)
Author
Age
Files
Lines
*
Update hardware procedure metadata
Anusha Reddy Rangareddygari
2017-10-04
70
-103
/
+103
*
Remove functionality from tp enable ridi and move it to nest enabled ridi
Christian Geddes
2017-10-02
3
-26
/
+47
*
Allow request fused mode bit when in HW fused mode
Dean Sanner
2017-09-22
1
-2
/
+4
*
ATTR_CHIP_EC_FEATURE_HW406337 support for Axone
Abhishek Agarwal
2017-09-12
1
-2
/
+2
*
resolve Zeppelin DMI channel framelock issues
Joe McGill
2017-09-12
2
-1
/
+20
*
Ensure SGPE is disabled and ensure writes are enabled during pm_suspend
crgeddes
2017-08-31
1
-9
/
+0
*
p9_sbe_tracearray: Add chip type detection to support changed p9c MC traces
Joachim Fenkes
2017-08-29
1
-47
/
+88
*
Move clearing of CPMMR PPM WRITE DISABLE so it called on all func cores
crgeddes
2017-08-24
1
-7
/
+9
*
Optimise RamCore put_reg & get_reg
spashabk-in
2017-08-23
1
-261
/
+194
*
Clear disable_ppm_writes bit on CPPM register prior to setting PFDLY
crgeddes
2017-08-18
2
-0
/
+8
*
Synchronous stopclk procedure for Quad
Soma BhanuTej
2017-08-16
2
-22
/
+33
*
p9_sbe_lpc_init: Fix LPC bus LRESET for DD2
Joachim Fenkes
2017-08-16
2
-64
/
+111
*
p9_sbe_common -- update TP LFIR to match RAS XML v95
Joe McGill
2017-08-10
1
-1
/
+1
*
L3 Update - p9_ram_core HWPs
Thi Tran
2017-08-08
2
-79
/
+100
*
p9_sbe_chiplet_pll_initf: Level 3
Joachim Fenkes
2017-07-26
2
-3
/
+3
*
p9_sbe_npll_setup: Level 3
Joachim Fenkes
2017-07-26
2
-4
/
+4
*
p9_sbe_npll_initf: Level 3
Joachim Fenkes
2017-07-26
2
-3
/
+3
*
p9_hcd_cache_dcc_skewadjust_setup.C
Anusha Reddy Rangareddygari
2017-07-26
1
-2
/
+2
*
TP, Nest FIR updates -- DD2 updates to match RAS XML
Joe McGill
2017-07-26
2
-9
/
+21
*
p9_sbe_tp_chiplet_init3: Level 3
Joachim Fenkes
2017-07-25
2
-3
/
+3
*
p9_sbe_tracearray: Nimbus DD2 updates
Joachim Fenkes
2017-07-24
1
-59
/
+132
*
p9_sbe_check_master_stop15: Level 3
Joachim Fenkes
2017-07-20
2
-9
/
+15
*
Optimized PPE FFDC collection framework
Amit Tendolkar
2017-07-19
1
-6
/
+16
*
updates for thread control, ramming with STOP enabled
Joe McGill
2017-07-19
1
-1
/
+9
*
Create dmi.pll.scan.initfile
Ben Gass
2017-07-14
4
-7
/
+100
*
p9_hcd_cache_dcc_skewadjust_setup
Anusha Reddy Rangareddygari
2017-07-14
1
-46
/
+15
*
Add PERV chiplet to MCGR 0
Anusha Reddy Rangareddygari
2017-07-13
1
-0
/
+5
*
mc_pll_bucket attribute
Anusha Reddy Rangareddygari
2017-07-12
1
-0
/
+10
*
dcc skew adjust procedure update
Anusha Reddy Rangareddygari
2017-07-12
1
-229
/
+248
*
Cumulus proc updates
Anusha Reddy Rangareddygari
2017-07-12
1
-45
/
+90
*
p9_sbe_chiplet_reset updates
Anusha Reddy Rangareddygari
2017-07-12
1
-0
/
+2
*
p9_{mem,sbe_chiplet}_pll_setup: Level 3
Joachim Fenkes
2017-07-11
2
-3
/
+3
*
p9_sbe_select_ex -- add option to skip HB checks
Joe McGill
2017-07-11
2
-4
/
+12
*
Restore backward compatibilty of SBE image with HB/HWSV
Sachin Gupta
2017-07-07
1
-0
/
+24
*
Update p9_sbe_chiplet_reset to support MV GSD2PIB
Abhishek Agarwal
2017-07-03
1
-0
/
+2
*
p9_sbe_select_ex -- skip new checks for b_single=false
Joe McGill
2017-07-03
1
-2
/
+2
*
p9_sbe_select_ex: add fused core booting support
Greg Still
2017-07-03
1
-31
/
+85
*
p9_tp_stopclocks: Don't raise CFAM FENCE2 to keep PERV chiplet accessible
Joachim Fenkes
2017-06-23
1
-1
/
+1
*
p9_sbe_tp_chiplet_init1: Set TP_TCPERV_SRAM_ENABLE_DC
Joe Dery
2017-06-23
1
-0
/
+5
*
Propagate "fused_core" IPL option into PU chip
Joachim Fenkes
2017-06-23
2
-2
/
+16
*
add support for OBUS PLL buckets
Joe McGill
2017-06-23
2
-14
/
+131
*
p9_fastarray: Level 3
Joachim Fenkes
2017-06-19
2
-8
/
+4
*
p9_sbe_tracearray: Level 3
Joachim Fenkes
2017-06-19
2
-36
/
+33
*
p9_common_stopclocks: Level 3
Joachim Fenkes
2017-06-19
2
-4
/
+16
*
Check Scratch Register 3 bit 7 and set new ATTR_SECURE_SETTINGS
Mike Baiocchi
2017-06-07
1
-4
/
+15
*
Added traces to figure out the infinite loop in the mpipl path
Raja Das
2017-06-05
1
-3
/
+6
*
p9_fastarray: Fix ABIST engines not running to completion
Joachim Fenkes
2017-06-02
1
-4
/
+4
*
p9_fastarray: Raise CTRL_CC_SDIS_DC_N during dump
Joachim Fenkes
2017-06-02
2
-0
/
+8
*
p9_sbe_tp_switch_gears, p9_sbe_gear_switcher: Level 3
Joachim Fenkes
2017-06-01
4
-9
/
+14
*
p9_sbe_common: Level 3
Joachim Fenkes
2017-06-01
2
-21
/
+48
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