TP, Nest FIR updates -- DD2 updates to match RAS XML

TP Pervasive LFIR
  - mark bit 21 recoverable to match XML specification
  - add Nimbus-only workaround for XBUS PLL lock reporting
  - adjust MEM PLL reset,setup routines to avoid generating spurious attention
    from MEM PLL

FBC IOE TL FIR
  - mask bits 9,12,15 to match XML specification
  - mark bits 56..58 checkstop to match XML specification

FBC IOO DL FIR
  - mask bits 56..59, 62..63 to match XML specification
  - mark bits 60..61 recoverable to match XML specification

IO OBUS FIR
  - mark bit 2 recoverable to match XML specification

CXA FIR
  - update initfile to handle change in number of implemented bits from
    Nimbus DD1 to DD2

NX CQ FIR
  - mark bits 6,16,20..21,23..24,28,39 checkstop to match XML specification
  - mark bit 11 recoverable to match XML specification changes

Change-Id: Ic954b2281d1d86ad91e7cd4952923af8c0fa0d8b
CQ: HW415692
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42909
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 21 insertions, 9 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
index 71b672aa..f59b0cd6 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -64,7 +64,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock(
 
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
-    const bool i_bypass);
+    const bool i_bypass,
+    const bool i_unmask);
 
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
@@ -85,6 +86,8 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
     uint8_t l_read_attr = 0;
     uint8_t l_bypass = 0;
     uint8_t l_use_dmi_buckets = 0;
+    uint8_t l_hw415692 = 0;
+
     FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ...");
 
     auto l_mc_io_func = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
@@ -102,6 +105,8 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
     FAPI_DBG("Reading ATTR_mc_sync_mode");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW415692, i_target_chip, l_hw415692));
+
     for (auto& mc : l_mc_io_func)
     {
         uint32_t l_chipletID = mc.getChipletNumber();
@@ -190,12 +195,13 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
     {
         // OBUS, XBUS, PCIe, MC
         uint32_t l_chipletID = targ.getChipletNumber();
+        bool l_unmask = !(l_hw415692 && (l_chipletID == XB_CHIPLET_ID));
 
         if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) ||
            (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) ||
            ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
         {
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(targ, l_bypass));
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(targ, l_bypass, l_unmask));
         }
     }
 
@@ -253,10 +259,12 @@ fapi_try_exit:
 ///
 /// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
 /// @param[in]     i_bypass           Leave PLL in bypass?
+/// @param[in]     i_unmask           Unmask PLL error reporting?
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
-    const bool i_bypass)
+    const bool i_bypass,
+    const bool i_unmask)
 {
     fapi2::buffer<uint64_t> l_data64;
     FAPI_INF("p9_sbe_chiplet_pll_setup_function: Entering ...");
@@ -281,10 +289,14 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
     //Setting ERROR_REG register value
     //ERROR_REG = 0xFFFFFFFFFFFFFFFF
     FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, 0xFFFFFFFFFFFFFFFF));
-    FAPI_DBG(" Unmasking pll unlock error in   Pcb slave config reg");
-    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_SLAVE_CONFIG_REG, l_data64));
-    l_data64.clearBit<12>();
-    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SLAVE_CONFIG_REG, l_data64));
+
+    if (i_unmask)
+    {
+        FAPI_DBG(" Unmasking pll unlock error in   Pcb slave config reg");
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_SLAVE_CONFIG_REG, l_data64));
+        l_data64.clearBit<12>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SLAVE_CONFIG_REG, l_data64));
+    }
 
     FAPI_INF("p9_sbe_chiplet_pll_setup_function: Exiting ...");
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
index deded1ea..8ef06bdb 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
@@ -76,7 +76,7 @@ const uint64_t PERV_LFIR_ACTION0[15] =
 
 const uint64_t PERV_LFIR_ACTION1[15] =
 {
-    0xF000000000000000ULL, // TP
+    0xF000040000000000ULL, // TP
     0xF000000000000000ULL, // N0
     0xF000000000000000ULL, // N1
     0xF000000000000000ULL, // N2
@@ -95,7 +95,7 @@ const uint64_t PERV_LFIR_ACTION1[15] =
 
 const uint64_t PERV_LFIR_MASK[15] =
 {
-    0x0FFFBC2BFC400000ULL, // TP
+    0x0FFFB82BFC400000ULL, // TP
     0x0FFFFFFFFFC00000ULL, // N0
     0x0FFFFFFFFFC00000ULL, // N1
     0x0FFFFFFFFFC00000ULL, // N2